Via-Aware Dogleg Routing Using Boolean Satisfiability

Abstract

Boolean Satisfiability (SAT)-based channel routing with via-aware pin doglegging is presented in this paper. The effect of the pin dogleg layout of connecting wires has been tested separately for input–output pins and output pins only with controlled use of vias for dogleg during detailed routing. Dogleg may reduce the channel width required for laying down all nets and hence decrease the total chip area. However, invalid selection of dogleg may increase the channel width or may identify a routable circuit as unroutable. Unwanted dogleg may also increase the use of vias (switches) required for changing the track from one to another and may create a congested area with vias. Congested via may introduce lithographic printing problem during manufacturing and power leakage problem. The proposed technique considers all these constraints to provide an optimal result and gives a compact layout for a circuit with controlled via for doglegging. The results obtained show that pin dogleg layout produces a more compact layout for connecting wires with supervised via when compared to dogleg-free routing or doglegged routing with unsupervised via for some standard benchmark circuits. It yields optimal results with reduced number of tracks in a channel and smaller chip size.