Методы анализа выполнимости булевых формул для современных задач систем автоматизации проектирования в микроэлектронике

Abstract

Currently, the methods based on a Boolean satisfiability (SAT) problem are one of the efficient approaches to solving the problem of Boolean matching and the equivalence checking of digital circuits. In combination with classic routing algorithms and optimization techniques, the SAT methods demonstrate the results exceeding the classic routing algorithms by the operation speed and the quality of obtained results. In the paper, the analysis of the modern practice of using the SAT methods in the CAD systems for VLSI has been performed. The examples of modern SAT approaches to the problems of the formal equivalence checking of digital circuits descriptions within the technological mapping framework and to the routing problem as a part of the FPGA design flow have been considered. The algorithm of the detailed routing of the FPGA switching blocks using the satisfiability problem has been developed and presented. The results of its work have been demonstrated on the example of the programmable logic block of the domestic made integrated circuit 5400TP094. The block has the island architecture, where the configurable logic blocks and switching blocks form a regularly repeated layout template. The properties of the chosen classic architecture permit to expand the region of presented algorithm to the entire class of island style FPGA. The algorithm has been tested on the project benchmarks ISCAS-85, ISCAS-89 and LGSynth-89. The comparison of the developed SAT-based algorithm with the well-known routing algorithm Pathfinder by criteria of the elapsed time and the achieved portion of routed nets in the switching blocks is presented. It has been determined that the considered Boolean satisfiability methods for the routing problem are capable to prove the circuit unroutability, unlike the algorithm Pathfinder which results can only implicitly indicate it. The paper demonstrates that the application of more efficient SAT solver significantly accelerates work of the suggested detailed routing algorithm.