A Fully Integrated 0.055% INL X-ray CCD Readout ASIC with Incremental <inline-formula> <tex-math notation="LaTeX">$\Delta \Sigma {\text{ADC}}$</tex-math> </inline-formula>

Abstract

A fully integrated 100 kHz X-ray charge coupled device (CCD) readout application specific integrated circuit (ASIC) employing delta sigma ( $\Delta \Sigma $ ) digitization is presented. To achieve high linearity with small chip size and low power consumption, the correlated double sampling (CDS) is realized by the $\Sigma \Delta{\rm ADC}$ instead of the analog front end (AFE) as in conventional CCD readout circuits. Besides, the proposed decimation filter features simple structure and eases the integration. The chip is fabricated in $0.35 \upmu\hbox{m}$ CMOS technology and the measured integral nonlinearity (INL) throughout the input dynamic range of ASIC is 0.055% with $35.1 \pm 0.3 \upmu\hbox{V}$ input referred noise. A CCD detection system is built and tested with the sensitivity of CCD being $4 \upmu\hbox{V}/\hbox{e}^-$ . The integration test results show that the readout noise is $11.8 \hbox{e}^ {-} $ at 100 kHz readout pixel rate and the achieved energy spectrum resolution is $168 \hbox{eV} \pm 4.7 \hbox{eV}$ (Full Width at Half Maximum: FWHM) at 5.9 keV.