Small Gate Leakage Research Articles

Low-Energy Path to Dense HfO2 Thin Films with Aqueous Precursor

New, stable aqueous solutions have been developed for the deposition of high-quality HfO2 thin films. The low ionic strength of the solution relative to a stoichiometric salt provides the means to directly spin coat a film without organic additives. Peroxide mediates particle interaction in the solution, while enabling relatively low-energy pathways for condensation of the precursor species to a film. Film structure, chemistry, and density are investigated by X-ray diffraction, FT-IR, electron-probe microanalysis, SEM, and X-ray reflectivity. Results from these measurements collectively reveal that smooth and dense HfO2 films are readily produced from the precursors with annealing at moderate temperatures. Optical properties of the films are studied by spectroscopic ellipsometry and transmission/reflection measurements. The observed refractive indices (1.89−1.93) are comparable to those achieved via vapor deposition techniques. Dielectric properties are evaluated through integration of the films into capacitors and thin film transistors. Performance as capacitor dielectrics is characterized by leakage current densities <10 nA/cm2 (at 1 MV/cm) and breakdown fields up to 5.5 MV/cm. As gate dielectrics in thin film transistors with amorphous indium gallium zinc oxide channels, the films exhibit small gate leakage, enabling transistor performance with incremental mobilities near 13 cm2/V·s.

Nonalloyed ohmic contact of AlGaN/GaN HEMTs by selective area growth of single‐crystal n+‐GaN using plasma assisted molecular beam epitaxy

AbstractSelective area growth (SAG) based on plasma assisted molecular beam epitaxy (PAMBE) was demonstrated to be effective to achieve low contact resistance for nonalloyed ohmic metals. An AlGaN/GaN high‐electron mobility transistor (HEMT) using SAG by PAMBE with nonalloyed ohmic metals and recessed drain/source structure exhibited a low specific contact resistance of 3.7 × 10−5 Ω cm2, high‐peak drain current of 604 mA/mm, and small gate leakage current of 3.4 µA. These results demonstrate that SAG by PAMBE produces nonalloyed HEMT with comparable or more favorable electric performance versus conventional alloyed counterpart while avoiding problems of the latter resulting from high‐temperature annealing.

Impact of Gate Engineering on Gate Leakage Behavior of Nano Scale MOSFETs with High-k Dielectrics

This paper discusses the gate leakage current characteristics based on gate tunnel model for different device structure having high-k dielectric as a gate dielectric and/or a spacer. In this study, a device structures are characterized to reduce the gate leakage current based on gate dielectric and the spacer structures. Several structures were also studied for other electrical performance parameters like on current, off current, drain induced barrier lowering (DIBL), subthreshhold slope(SS). The device structure in which the high-k dielectric extends to the bottom of the oxide spacers showed the smallest gate leakage current while the device structure in which gate dielectric is of high-k material and spacer is of silicon dioxide showed the best DIBL, SS, on current and off current characteristics.

Electrical Characteristics of Pulsed Laser Deposited SrTiO3 on TiO2 Buffered AlGaN/GaN

SrTiO3 (STO) dielectric film with TiO2 buffer was grown on AlGaN/GaN heterostructures by pulsed laser deposition (PLD). X-ray diffraction (XRD) characterization showed that highly (111)-oriented STO film was fabricated at 500°C with the TiO2 buffer. Electrical properties of MOS-HFET with 100 nm STO and 10 nm TiO2 buffer were investigated. The current-voltage (I-V) curves displayed a lower of 4.6×10−10 A at a gate voltage of −4 V, comparing with HFETs without STO/TiO2 dielectric layer. From the capacitance-voltage (C-V) curves, the total interfacial states density was estimated to be less than 1012 cm−2eV−1.The dielectric constant was determined to be 110, and Equivalent Oxide Thickness (EOT) was about 3.6 nm. It was found that the introduction of buffer led to the following effects: (1) inducing the crystal of STO at a low temperature, (2) decreasing the interfacial states density, (3) achieving small gate leakage current density. Thus, the integrated MOS-HFET can show good electrical characteristics for further possible applications.

P-Type ECRL Circuits for Gate-Leakage Reduction in Nanometer CMOS Processes with Gate Oxide Materials

With the decrease of the power supply voltage, the thickness of the gate oxide has been also scaled down in CMOS technologies using gate oxide materials. The leakage dissipation through the gate oxide is becoming an important component of power consumption in currently used nanometer CMOS processes without metal gate structure. Base on the fact that PMOS transistors have an order of magnitude smaller gate leakage than NMOS ones, this paper propose a P-type efficient charge recovery logic (P-ECRL) to reduce leakage dissipations in nanometer CMOS processes with gate oxide materials. For an example, a J-K flip-flop and a mode-10 counter using four-phase P-ECRL circuits are verified. All circuits are simulated using 90nm and 45nm CMOS processes with gate oxide materials. The proposed P-ECRL circuits show significant improvement in terms of power consumption over the traditional N-type ECRL counterparts.

Impact of Al2O3 incorporation on device performance of HfO2 gate dielectric AlGaN/GaN MIS‐HFETs

AbstractWe report the effects of Al2O3 interfacial layer incorporation on the dc performance of AlGaN/GaN metal‐insulator‐semiconductor field effect transistors (MIS‐HFETs) using HfO2 as the gate dielectric and surface passivation layer. The HfO2/Al2O3 bi‐layer MIS‐HFETs exhibit a larger maximum drain current by ∼8.5%, larger gate voltage swing by ∼6.3%, and smaller gate leakage by 4∼5 times, compared to the HfO2 single layer MIS‐HFETs at room temperature. Furthermore, the HfO2/Al2O3 transistors are observed to have better thermal stability than the HfO2 transistors, and the estimated lifetime (in hour) of the former is longer than that of the latter by over an order of magnitude from 25 to 150 °C (© 2010 WILEY‐VCH Verlag GmbH &amp; Co. KGaA, Weinheim)

Forms and behaviour of vacuum emission electronic devices comprising diamond or other carbon cold cathode emitters

Nanocarbon-derived electron emission devices, specifically nanodiamond lateral field emission (FE) diodes and gated carbon nanotube (CNT) triodes, are new configurations for robust nanoelectronic devices. These novel micro/nanostructures provide an alternative and efficient means of accomplishing electronics that are impervious to temperature and radiation. For example, nitrogen-incorporated nanocrystalline diamond has been lithographically micropatterned to use the material as an electron field emitter. Arrays of laterally arranged 'finger-like' nanodiamond emitters constitute the cathode in a versatile diode configuration with a small interelectrode separation. A low diode turn-on voltage of 7V and a high emission current of 90 microA at an anode voltage of 70V (electric field of approx. 7V microm(-1)) are reported for the nanodiamond lateral device. Also, a FE triode amplifier based on aligned CNTs with a low turn-on voltage and a small gate leakage current has been developed.

Field emission devices for advanced electronics comprised of lateral nanodiamond or carbon nanotube emitters

Nanocarbon-derived electron emission devices, specifically, nanodiamond lateral field emission diodes and gated carbon nanotube triodes are new configurations for robust nanoelectronic devices. These novel micro/nanostructures provide an alternative and efficient means of accomplishing electronics that are impervious to temperature and radiation. Nitrogen-incorporated nanocrystalline diamond has been lithographically micropatterned to utilize the material as an electron field emitter. Arrays of laterally arranged “finger-like” nanodiamond emitters constitute the cathode in a versatile diode configuration with small interelectrode separation. Nanodiamond lateral tip conditioning techniques are employed to improve emission and the subsequent device performance discussed. A low diode turn-on voltage of 7 V and a high emission current of 90 μA at an anode voltage of 70 V (electric field of ∼ 7 V/μm) is reported for the nanodiamond lateral device. Also, the development of a field emission triode amplifier based on aligned carbon nanotubes (CNTs) with low turn-on voltage and small gate leakage current, utilizing a dual-mask microfabrication process is reported. The2 × 20 μm CNT triode array displays a gate turn-on voltage of ∼ 44 V, and low gate currents less than 3% of the anode currents. The low gate leakage currents observed confirmed the effectiveness of the convex-shaped gated CNT emitter in alleviating the cathode-gate leakage problem that compromises the operation of a field emission triode.

Characteristics of Self-Aligned Gate-First Ge p- and n-Channel MOSFETs Using CVD $\hbox{HfO}_{2}$ Gate Dielectric and Si Surface Passivation

The electrical properties of p- and n-MOS devices fabricated on germanium with metal-organic chemical-vapor-deposition HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> as gate dielectric and silicon passivation (SP) as surface treatment are extensively investigated. Surface treatment prior to high-K deposition is critical to achieve small gate leakage currents as well as small equivalent oxide thicknesses. The SP provides improved interface quality compared to the treatment of surface nitridation, particularly for the gate stacks on p-type substrate. Both Ge p- and n-MOSFETs with HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2 </sub> gate dielectrics are demonstrated with SP. The measured hole mobility is 82% higher than that of the universal SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /Si system at high electric field (~0.6 MV/cm), and about 61% improvement in peak electron mobility of Ge n-channel MOSFET over the CVD HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2 </sub> /Si system was achieved. Finally, bias temperature-instability (BTI) degradation of Ge MOSFETs is characterized in comparison with the silicon control devices. Less negative BTI degradation is observed in the Ge SP p-MOSFET than the silicon control devices due to the larger valence-band offset, while larger positive BTI degradation in the Ge SP n-MOSFET than the silicon control is characterized probably due to the low-processing temperature during the device fabrication

Electrical properties and reliability of HfO2gate-dielectric MOS capacitors with trichloroethylene surface pretreatment

Trichloroethylene (TCE) pretreatment of Si surface prior to HfO2 deposition is employed to fabricate HfO2 gate-dielectric MOS capacitors. Influence of this processing procedure on interlayer growth, HfO2/Si interface properties, gate-oxide leakage and device reliability is investigated. Among the surface pretreatments in NH3, NO, N2O and TCE ambients, the TCE pretreatment gives the least interlayer growth, the lowest interface-state density, the smallest gate leakage and the highest reliability. All these improvements should be ascribed to the passivation effects of Cl2 and HCl on the structural defects in the interlayer and at the interface, and also their gettering effects on the ion contamination in the gate dielectric.

Impact of surface treatment under the gate on the current collapse of unpassivated AlGaN/GaN heterostructure field-effect transistors

Unpassivated GaN/AlGaN/GaN/SiC heterostructure field-effect transistors were fabricated on intentionally undoped and 5 × 1018 cm−3 modulation-doped material structures. The influence of surface treatment before gate metallization on the gate leakage and drain current collapse of the devices was observed. In the case of a short HCl treatment (∼5 s), a relatively small gate leakage (<10−6 A mm−1 at −6 V gate bias) but large current collapse (∼30% after applying 5 µs wide pulses) were measured. On the other hand, devices with a longer surface treatment (15–20 s) showed an increased gate leakage (>10−4 A mm−1) and a simultaneously negligible current collapse (<5%). This effect is qualitatively similar in devices prepared on the undoped and doped heterostructures. It is assumed that a thin interfacial oxide layer under the gate might be responsible for a lower leakage current and a larger current collapse of the devices.

Performance of GaAs JFET at a Cryogenic Temperature for Application to Readout Circuit of High-Impedance Detectors

A GaAs junction field effect transistor (JFET) is a promising candidate for the cryogenic electronics of high-impedance sensitive photoconductors because of its low-noise at low frequencies. This GaAs JFET has advantages compared with other type of FETs, such as no kink phenomena or hysteresis in its current-voltage (I-V) characteristics, small gate leakage currents, and minute capacitance. We report on the noise spectra and leakage current of a SONY n-type GaAs FET in a high-impedance configuration where the gate terminal was surrounded by high-impedance devices at a cryogenic temperature, i.e., 4.2 K. In the high-impedance configuration, we obtained a low noise level and low leakage current of 0.5 /spl mu/V/Hz/sup 1/2/ at 1 Hz and 4.6/spl times/10/sup -19/ A. This result implies that the GaAs JFET is suitable for cryogenic readout electronics. We also discuss the source of the random telegraph signal and the 1/f noise in the GaAs JFET at cryogenic temperatures.

Atomic Layer Deposition of High-&amp;lt;tex&amp;gt;$kappa$&amp;lt;/tex&amp;gt;Dielectric for Germanium MOS Applications—Substrate Surface Preparation

In this letter, we present the use of atomic layer deposition (ALD) for high-/spl kappa/ gate dielectric formation in Ge MOS devices. Different Ge surface cleaning methods prior to high-/spl kappa/ ALD have been evaluated together with the effects on inserting a Ge oxynitride (GeO/sub x/N/sub y/) interlayer between the high-/spl kappa/ layer and the Ge substrate. By incorporating a thin GeO/sub x/N/sub y/ interlayer, we have demonstrated excellent MOS capacitors with very small capacitance-voltage hysteresis and low gate leakage. Physical characterization has also been done to further investigate the quality of the oxynitride interlayer.

Delta-doped AlGaN/GaN metal–oxide–semiconductor heterostructure field-effect transistors with high breakdown voltages

The fabrication and dc characteristics of AlGaN/GaN-based heterostructure field-effect transistors (HFETs) by employing the δ-doped barrier and the SiO2 insulated gate are reported. The device grown on sapphire substrate has a high drain-current-driving and gate-control capabilities as well as a very high gate-drain breakdown voltage of 200 V for a gate length of 1 μm and a source-drain distance of 3 μm. The incorporation of the SiO2 insulated gate and the δ-doped barrier into HFET structures reduces the gate leakage and improves the two-dimensional channel carrier mobility, and thereby allows one to take the inherent advantage of AlGaN/GaN HFETs with relatively high Al contents—the device structure is capable to deliver higher electron density (or drain current density) yet ensures an excellent pinch-off property as well as small gate leakage current. These characteristics indicate a great potential of this structure for high-power-microwave applications.

Novel extension of neu-MOS techniques to neu-GaAs

The neuron-MOS (neu-MOS) transistor, recently discovered by Shibata and Ohmi in 1991 [T. Shibata, T. Ohmi, International Electron Devices Meeting, Technical Digest, 1991] uses capacitively coupled inputs onto a floating gate. Neu-MOS enables the design of conventional analog and digital integrated circuits with a significant reduction in transistor count [L.S.Y. Wong, C.Y. Kwok, G.A. Rigby, in: Proceedings of the 1997 IEEE Custom Integrated Circuits Conference, 1997; B. Gonzales, D. Abbott, S.F. Al-Sarawi, A. Hernandez, J. Garcia, J. López, in: Proceedings of the XIII Design of Circuits and Integrated Systems Conference (DCIS'98), 1998, pp. 62–66]. Furthermore, neu-MOS circuit characteristics are relatively insensitive to transistor parameter variations inherent in all MOS fabrication processes. Neu-MOS circuit characteristics depend primarily on the floating gate coupling capacitor ratios. It is also thought that this enhancement in the functionality of the transistor, i.e. at the most elemental level in circuits, introduces a degree of flexibility that may lead to the realisation of intelligent functions at a system level [T. Ohmi, T. Shibata, in: Proceedings of the 20th International Conference on Microelectronics, vol. 1, 1995, pp. 11–18]. This paper extends the neu-MOS paradigm to complementary gallium arsenide based on HIGFET transistors. The design and HSPICE simulation results of a neu-GaAs ripple carry adder are presented, demonstrating the potential for very significant transistor count and area reduction through the use of neu-GaAs in VLSI design. Preliminary simulations indicate a reduction of a factor of four in transistor count for the same power dissipation as conventional complementary GaAs. The small gate leakage is shown to be useful in eliminating unwanted charge build-up on the floating gate.

Complementary neu-GaAs structure

A neu-MOS like transistor structure using complementary GaAs HIGFET transistors, neu-GaAs, which uses capacitively coupled inputs onto a floating gate is presented. The design and simulation results of a neu-GaAs ripple carry adder are presented, demonstrating the potential for a very significant reduction in transistor count and area for equal power dissipation, through the use of neu-GaAs in VLSI design. A neu-GaAs design is presented which does not require floating gate initialisation due to the presence of a small gate leakage current in the HIGFET structure.

Fabrication of a lateral field emission triode with a high current density and high transconductance using the local oxidation of the polysilicon layer

We have proposed and fabricated a lateral type polysilicon field emission triode using conventional photolithography and a LOCOS (local oxidation of polysilicon) in a lateral direction. The techniques employed in this study are very simple and allow for good reproducibility both in shaping sharp electrode tips and controlling the short cathode-to-gate inter-electrode distance. The devices exhibit excellent electrical characteristics such as a low turn-on voltage of 14 V at V/sub GC/=0 V, a stable high emission anode current (I/sub A/) of /spl mu/A/triode over 90 hours with a relatively small gate leakage current (I/sub G/) of 0.23 /spl mu/A/triode (I/sub A//I/sub G//spl ges/400), and large transconductance (g/sub m/) of 57 /spl mu/S/5 triode at v/sub GC/=5 V and V/sub AC/=26 V. These superior field emission characteristics are believed to be due to an increased field enhancement effect which is related to the sharp cathode and gate tips shaped by the LOCOS as well as the high aspect ratio (tip height/radius of tip end) of the cathode tip.

High density and high mobility transport characteristics in gated undoped GaAsAl/ xGa 1−xAs heterostructures

The two-dimensional electron gas which is formed at the interface in undoped GaAsAl xGa 1−xAs heterostructures by the electric field generated by a top gate is studied. The barrier region consists of an Al 0.3Ga 0.7As/Al 0.5Ga 0.5As superlattice to prevent undesirable tunneling through the barrier. Therefore, we are able to achieve high electron densities exceeding 10 16 m −2 with sufficient small gate leakage currents in a MISFET like device for the first time. Despite the high electron density in the sample rather high mobilities of about 100 m 2 V s −1 can be maintained at low temperatures. The population of the second subband is studied from Shubnikov-de Haas measurements in these devices. The role of intersubband scattering is important for understanding the magneto-transport experiments.

Transport in gated undoped GaAs/AlxGa1−xAs heterostructures in the high density and high mobility range

The two-dimensional electron gas with electron densities higher than 1016 m−2 which is formed at the interface in undoped GaAs/AlxGa1−xAs heterostructure by the electric field generated by a top gate is studied. Despite the high electron density in the sample, rather high mobilities of about 100 m2/Vs can be achieved with sufficient small gate leakage currents. The population of the second subband is studied from Shubnikov-de Haas measurements in these devices.

Formation of two-dimensional electron and hole gases in undoped AlxGa1−xAs/GaAs heterostructures

Two-dimensional electron or hole gases (2DEG or 2DHG) are confined at the same interface in an undoped heterostructure by an electric field generated by a top gate. The combination of ion-implanted ohmic regions, an undoped heterostructure with superlattice barriers, and a metal gate is used to fabricate structures by a conventional process without self-alignment. High-quality 2DEG and 2DHG with a carrier density up to 8×1011 cm−2 are formed with a small gate leakage current. Switching between 2DEG and 2DHG at the same heterointerface is achieved by changing the sign of the gate voltage.