Small Circuit Area Research Articles

Wire Length-Matching Aware Placement Method for Rapid Single Flux Quantum Logic Circuits

This paper proposes a fast automatic gate placement method for gate-level-pipelined Rapid Single Flux Quantum (RSFQ) circuits that are designed to have a high throughput. In such circuits, the gates in a pipeline stage are placed in a column and wires are routed in the area between adjacent columns. In wire routing, wire length-matching is performed. The proposed method performs gate placement for a given netlist to minimize the sum of the maximum distance between connected gates in each pair of adjacent columns. It leads to short wire extensions in wire length matching for increasing the operation frequency and small circuit area. The proposed method consists of a recursive procedure including two placements, selecting a pivot column, and determining the gate placement in the pivot column. The netlist is divided into two netlists with the pivot column. The recursive procedure performs gate placements for the two divided netlist. It is repeated until the location of every gate is determined. We implemented a placement tool by the proposed method and performed the gate placement for three circuits including several hundreds of gates. The proposed placement was 14 to 40 times faster than a placement based on simulated annealing where the sum of the maximum distance between connected gates is approximately the same.

A compact dual‐band coupled‐microstrip‐slotline coupler with arbitrary power division ratios

In this paper, a novel dual-band coupler with arbitrary power division ratios using coupled-microstrip-slotlines (CMSLs) is proposed. It consists of only four CMSL sections and occupies a small circuit area due to the centric arrangement of the excitation ports. Different from the microstrip implemented edge-coupled-line, the odd and even modes of the CMSL are physically separated, this feature enables the compensation of their phase velocities, facilitates the control of their characteristic impedances, and reduces the design complexity of the dual-band coupler. Explicit design formula for the proposed coupler is developed. To verify the proposed concept, a dual-band CMSL coupler with an unequal power division ratio is designed and characterized.

A Pythagorean tree fractal shape stub-loaded resonator as a UWB bandpass filter with wide stopband

AbstractA compact ultrawideband (UWB) bandpass filter (BPF) is designed by harnessing the efficacy of a Pythagorean tree fractal shape stub-loaded resonator. The design inherently provides the passband transmission poles, which make it convenient to be used in wide passband filtering circuits. The number and the position of the resonating modes can be controlled by increasing the iterations of the Pythagorean tree, as analyzed using odd- and even-mode analysis. Design steps of the BPF are detailed. The designed UWB BPF takes up a small circuit area of (12.13 × 9.59) mm2. The proposed design is fabricated and measured to verify the simulated results. The stopband is extended up to 17.5 GHz with a maximum attenuation of 15 dB.

A Layout Design Flow for RSFQ Circuits Based on Cell Clustering and Mixed Wiring of JTLs and PTLs

An automated layout design flow for rapid single-flux-quantum circuits is proposed in this article. In order to realize small circuit area and low latency, both Josephson transmission lines (JTLs) and passive transmission lines (PTLs) are used for interconnects. Placement and routing are performed considering effective use of JTLs and PTLs. Logic cells are grouped into clusters, and JTLs are used inside clusters. PTLs are used among clusters. The placement process is composed of three steps: first, cell clustering, second, cell placement and JTL routing in each cluster, and third, cluster placement. After the placement process, routing among clusters are performed using PTLs. We applied the proposed design flow to sample circuits with several hundreds of gates. Though the circuit area is not fully optimized, the latency of the circuits designed by the proposed design flow are lower than those of the circuits designed manually.

Low-Voltage Gate-Leakage-Based Timer Using an Amplifier-Less Replica-Bias Switching Technique in 55-nm DDC CMOS

Energy-efficient timer circuits are required in numerous applications for periodic operations, such as performing measurements and communicating data. In this paper, we present a gate-leakage-based timer that utilizes an amplifier-less replica-bias switching technique to generate a stable frequency, which can operate at a low supply voltage. To guarantee a stable oscillation frequency in a small circuit area, the proposed design adopts an architecture that discharges a pre-charged capacitor through a resistive element (gate-leaking MOS capacitor) with a low-leakage switch. In the proposed switching technique, the low-voltage timer operates by tracking the discharging terminal of the capacitor and biasing the reference voltage of the switch unit, thereby enabling the minimization of the leakage current without the need for analog amplifier circuits. The high supply sensitivity of the timer is addressed by regulating the supply voltage using a native NMOS header (NNH). The proposed design is fabricated using the 55-nm deeply depleted channel (DDC) CMOS technology, which has a strong body coefficient and occupies an active circuit area of 0.0022 mm2. The measurements show that the proposed design can achieve an energy-per-cycle value of 25 pJ/cycle at a supply voltage of 350 mV when body biasing is applied. The measured Allan deviation floor is 200 ppm at room temperature. The timer exhibits an average temperature sensitivity of 810 ppm/°C for four samples. Moreover, a reduction in the supply sensitivity by a factor of 26 using the NNH is demonstrated in an active circuit area of 0.0034 mm2.

An all-digital frequency tunable IR-UWB transmitter with an approximate 15th derivative Gaussian pulse generator

This work presents a new frequency-tunable, OOK–modulated, impulse-radio ultra-wideband (IR-UWB) transmitter, where approximate 15th derivative Gaussian pulses are produced by a monopulse-synthesis pulse generator. The center frequency of our output UWB pulses can be easily adjusted between 4 and 9 GHz by controlling delay time. Thus, the whole UWB frequency band from 3.1 to 10.6 GHz can be covered and utilized. Since the proposed monopulse-synthesis pulse generator already includes a pulse shaping function, RF bandpass filters are not required, thus realizing the extremely low complexity and small circuit area. The proposed IR-UWB transmitter has been implemented and fabricated in a standard 0.18 μm CMOS 1p6m process. The power supply voltage is 1.8 V and the targeted data rate is 31.25 Mbps. Chip measurement results show that the power spectrum density conforms to the FCC spectrum masks, and the peak-to-peak voltage of output UWB pulses is 56 mV. In addition, the core area of the chip is 0.02 mm2, the measured frequency tuning range is 3.1–10.6 GHz, and the measured energy dissipation is only 12.5 pJ/bit. Compared to the state-of-the-art designs in the literature, the chip area and tunable frequency range are improved by at least 33% and 53%, respectively.

Design of a Self-Controlled Dual-Oscillator-Based Supply Voltage Monitor for Biofuel-Cell-Combined Biosensing Systems in 65-nm CMOS and 55-nm DDC CMOS.

A supply voltage monitor (SVM) with self-controlled dual-oscillator-based architecture is proposed herein for biosensing systems combined with a biofuel cell (BFC) in this paper. The output of the BFCs can be used to monitor the biological signals while powering the BFC-combined biosensing systems. Thus, the SVM is designed to convert the change in the supply voltage (V DD) into a code. The architecture of the proposed SVM allows self-controlled periodic operation without external signals. Furthermore, the frequency subtraction technique that uses two oscillators employing gate-leakage-based architecture with different frequency sensitivities to V DD allows accurate code generation with low power consumption and a small circuit area for supply voltage monitoring. The proposed SVM is fabricated using two different CMOS process technologies, including 65-nm CMOS and 55-nm deeply depleted channel (DDC) CMOS. The implementation of the 65-nm CMOS obtains an operating V DD range of 250mV (0.75-1V), draws a standby power consumption of 1.4 nW at 0.75-V V DD, exhibits a resolution of 2.4mV with a nonlinearity error of -8.4/ +12.1mV, and occupies a circuit area of 0.0047mm2. Meanwhile, the implementation of the 55-nm DDC CMOS for low-voltage operation achieves an operating V DD range of 300mV (0.225-0.525V), draws a standby power consumption of 32.5 nW at 0.25-V V DD, exhibits a resolution of 0.94mV with a nonlinearity error of -15.2/ +14mV, and occupies a circuit area of 0.0032mm2.

Systematic synthesis of approximate adders and multipliers with accurate error calculations

In this study, we perform logic synthesis and area optimization of approximate ripple-carry adders and Wallace-tree multipliers with a given error constraint. We first implement approximate 1-bit adders having different error rates as building blocks of the proposed multi-bit adders and multipliers. In implementations, we exploit offsetting errors in carry and sum outputs of the adders. Also we take into account the probability of occurrence of input assignments. Using the implemented 1-bit adders, we systematically synthesize multi-bit adders and multipliers proceeding from the least to the most significant bits. We design the ripple-carry adders such that their successive 1-bit approximate adders cannot produce build-up errors. We design the Wallace-tree multipliers by considering the fact that their building blocks of 1-bit adders might have different probabilities of occurrence for different input assignments. As a result, the proposed adders and multipliers, implemented using the Cadence Genus tool with TSMC 0.18μ m CMOS technology, offer in average a 25% smaller circuit area, and correspondingly power consumption, compared to the circuits proposed in the literature by satisfying the same error constraint. We also evaluate the adders and multipliers in image processing applications as well as within artificial neural networks.

Study on Single Flux Quantum Floating-Point Divider Based on Goldschmidt's Algorithm

We investigate a Goldschmidt's single flux quantum (SFQ) floating-point divider that is suitable for the implementation using the bit-serial pipelined SFQ circuit. We designed the bit-serial SFQ divider that outputs the 11-bit quotient. The simulation results show correct operation at the frequency of 50-GHz and bias margin of 80%–125%. We also estimated dependence of latency and the number of Josephson junctions on accuracy of outputs. According to the estimation, double-precision SFQ divider can be designed using 27 000 Josephson junctions, which can be implemented on one chip using the current SFQ circuit fabrication technology. Because of the small circuit area and multiplier-based hardware architecture, the investigated divider can be applied to build an SFQ graphical processing unit.

New compact low-pass filter (LPF) using cascaded square open loop resonator

This article introduces a new design technique of low-pass filter using cascaded square open loop resonator (SOLR) for the multi-wireless communication system. In the design procedure, a half-wavelength SOLR is realized with 6 GHz to meet the desired LPF cut off frequency. As the resonator is fed by a direct connection of 50-ohm input/output ports, the structure is directly transferred into a second-order low-pass filter with elliptic behavior. An equivalent circuit is extracted and its lumped elements are computed to support the proposed second-order LPF. Based on the equivalent circuit, highly selective third and fifth-order LPFs with wide rejection band are developed. To achieve this development several SOLR are cascaded by a direct connection. The designed filters are implemented on a grounded substrate which has relative permittivity of 6.15 and thickness of 0.508 mm. To verify the design concept, a third-order LPF using two cascaded SOLRs is designed, simulated, fabricated and measured. The filter responses obtained from theory, simulation, and measurement show good agreement. The filter has very small circuit area about 31 mm2 excluding the input/output feeding ports.

Complexity of Simple, Switched and Skipped Chaotic Maps in Finite Precision.

In this paper we investigate the degradation of the statistic properties of chaotic maps as consequence of their implementation in a digital media such as Digital Signal Processors (DSP), Field Programmable Gate Arrays (FPGA) or Application-Specific Integrated Circuits (ASIC). In these systems, binary floating- and fixed-point are the numerical representations available. Fixed-point representation is preferred over floating-point when speed, low power and/or small circuit area are necessary. Then, in this paper we compare the degradation of fixed-point binary precision version of chaotic maps with the one obtained by using floating point 754-IEEE standard, to evaluate the feasibility of their FPGA implementation. The specific period that every fixed-point precision produces was investigated in previous reports. Statistical characteristics are also relevant, it has been recently shown that it is convenient to describe the statistical characteristic using both, causal and non-causal quantifiers. In this paper we complement the period analysis by characterizing the behavior of these maps from an statistical point of view using cuantifiers from information theory. Here, rather than reproducing an exact replica of the real system, the aim is to meet certain conditions related to the statistics of systems.

Subleq $_\circleddash$ : An Area-Efficient Two-Instruction-Set Computer

Applications with strict resource/power constraints demand the research and development of area-efficient processor designs that deliver reasonably good performance with small circuit area. While the ARM and RISC-V instruction set architecture (ISAs) are lightweight alternatives to $\boldsymbol \times 86$ , they nevertheless consume considerable circuit area and power. In this letter, we return to a fundamental question: how area efficient can a processor be while retaining the property of being “turing complete” (i.e., capable of realizing any computation)? Beginning with a recently published one-instruction-set computer, that uses a minimal amount of resources, we consider adding a second instruction to the instruction set and justify the choice of such an instruction. An experimental study illustrates the benefits of our ISA extension in terms of performance at minimal area cost.

Design and evaluation of area-efficient and wide-range impedance analysis circuit for multichannel high-quality brain signal recording system

To enable chronic and stable neural recording, we have been developing an implantable multichannel neural recording system with impedance analysis functions. One of the important things for high-quality neural signal recording is to maintain well interfaces between recording electrodes and tissues. We have proposed an impedance analysis circuit with a very small circuit area, which is implemented in a multichannel neural recording and stimulating system. In this paper, we focused on the design of an impedance analysis circuit configuration and the evaluation of a minimal voltage measurement unit. The proposed circuit has a very small circuit area of 0.23 mm2 designed with 0.18 µm CMOS technology and can measure interface impedances between recording electrodes and tissues in ultrawide ranges from 100 Ω to 10 MΩ. In addition, we also successfully acquired interface impedances using the proposed circuit in agarose gel experiments.

Circuit design of Clos-based on-chip interconnection networks

Single-hop non-blocking networks have the advantage of providing uniform latency and throughput, which is important for cache-coherent network-on-chip systems. This paper focuses on high performance circuit designs of multi-stage non-blocking networks as alternatives to crossbars. Existing work shows that Benes networks have much lower transistor count and smaller circuit area but longer delay than crossbars. To reduce the timing delay, we propose to design the Clos network built with larger size switches. Using less than half number of stages than the Benes network, the Clos network with 4×4 switches can significantly reduce the timing delay. The circuit designs of both Benes and Clos networks in different sizes are conducted considering two types of implementation of the configurable switch: with N-type metal-oxide-semiconductor logic (NMOS) transistors only and full transmission gates (TGs). The layout and simulation results under 45nm technology show that the TG-based implementation demonstrates much better signal integrity than its counterpart. Clos networks achieve average 60% lower timing delay than Benes networks with even smaller area and power consumption.

All-Digital Time-Domain CMOS Smart Temperature Sensor with On-Chip Linearity Enhancement.

This paper proposes the first all-digital on-chip linearity enhancement technique for improving the accuracy of the time-domain complementary metal-oxide semiconductor (CMOS) smart temperature sensor. To facilitate on-chip application and intellectual property reuse, an all-digital time-domain smart temperature sensor was implemented using 90 nm Field Programmable Gate Arrays (FPGAs). Although the inverter-based temperature sensor has a smaller circuit area and lower complexity, two-point calibration must be used to achieve an acceptable inaccuracy. With the help of a calibration circuit, the influence of process variations was reduced greatly for one-point calibration support, reducing the test costs and time. However, the sensor response still exhibited a large curvature, which substantially affected the accuracy of the sensor. Thus, an on-chip linearity-enhanced circuit is proposed to linearize the curve and achieve a new linearity-enhanced output. The sensor was implemented on eight different Xilinx FPGA using 118 slices per sensor in each FPGA to demonstrate the benefits of the linearization. Compared with the unlinearized version, the maximal inaccuracy of the linearized version decreased from 5 °C to 2.5 °C after one-point calibration in a range of −20 °C to 100 °C. The sensor consumed 95 μW using 1 kSa/s. The proposed linearity enhancement technique significantly improves temperature sensing accuracy, avoiding costly curvature compensation while it is fully synthesizable for future Very Large Scale Integration (VLSI) system.

A novel tunable microwave filter integrated power dividers using liquid crystal

ABSTRACTThis article presents design considerations of a tunable microwave filter integrated power divider based on highly anisotropic liquid crystals (LCs), which helps to reduce the circuit size. The proposed device comprising a thin LC layer between a ground plane and a directly coupled inverted microstrip line exhibits the equal power splitting function with a tunable bandpass response. The integrated device results in sharp rejection and smaller circuit area, as compared with the cascaded connection of an equal power divider and tunable microwave filter. © 2015 Wiley Periodicals, Inc. Microwave Opt Technol Lett 55:2539–2543, 2015

Image segmentation of pyramid style identifier based on Support Vector Machine for colorectal endoscopic images.

With the increase of colorectal cancer patients in recent years, the needs of quantitative evaluation of colorectal cancer are increased, and the computer-aided diagnosis (CAD) system which supports doctor's diagnosis is essential. In this paper, a hardware design of type identification module in CAD system for colorectal endoscopic images with narrow band imaging (NBI) magnification is proposed for real-time processing of full high definition image (1920 × 1080 pixel). A pyramid style image segmentation with SVMs for multi-size scan windows, which can be implemented on an FPGA with small circuit area and achieve high accuracy, is proposed for actual complex colorectal endoscopic images.

Miniaturized lowpass filter with ultra-wide stopband using dual-plane defected structures

A miniaturized lowpss filter (LPF) with ultra-wide stopband is proposed by using the complementary rectangle split ring defected microstrip structure (CRSR-DMS) and the quad U-shaped defected ground structure (QU-DGS). The presented CRSR-DMS can provide a sharp rejection rate and two obvious attenuation poles while the QU-DGS can produce four independently controlled transmission zeros. Based on the characteristics of the defected structures, the proposed LPF is constructed by using four cascaded CRSR-DMS units and four cascaded QU-DGS units. The measurement result of the designed filter with 3 dB cut-off frequency at 2.0 GHz shows that the obtained 20 dB rejection band ranges from 2.12 GHz to more than 20 GHz within a small circuit area of 0.73λg * 0.13λg, λg being the guided wavelength at 2.12 GHz.

40-nm Embedded Split-Gate MONOS (SG-MONOS) Flash Macros for Automotive With 160-MHz Random Access for Code and Endurance Over 10 M Cycles for Data at the Junction Temperature of 170 $^{\circ}$C

First-ever 40-nm embedded split-gate MONOS (SG-MONOS) flash macros for automotive micro-controller unit (MCU) have been successfully developed. A SG-MONOS cell realizes high performance with low power consumption and intrinsically high data reliability thanks to the combination of split-gate and charge-trapping structure. In addition, newly developed circuit techniques greatly enhance the advantages of SG-MONOS cells and enable fast and reliable operations even at the junction temperature (Tj) of 170°C with small peripheral circuit area; 1) a sense amplifier with digital offset cancellation (SA-DOC) provides fast read operation over 160 MHz; 2) adaptable program current control scheme (APCCS) and intelligent erase scheme (IES) significantly decrease the program and erase time, which also results in improving the memory cells' reliability; and, 3) 3-D stacked unit capacitors achieve area-efficient charge pump. Two types of embedded flash (eFlash) macros with these technologies, code macro of 2 MB and data macro of 64 KB, were fabricated in a 40-nm eFlash process. The code macro demonstrates the capability of 160-MHz random read operation at Tj= 170°C, reaching 5.1 GB/s read throughput by simultaneous 256 bits read-out from two code macros. The data macro achieves the program/erase endurance over 10 million cycles at Tj= 170°C without any software-assisted techniques.

A 3–5 GHz low-power high-speed radiated power tuning UWB transmitter

To satisfy the different radiated power requirements for the ultra-wideband (UWB) data transmitting in the implantable electronic devices or the wireless component interconnections, a novel low-power high-speed UWB transmitter with radiated power tuning was proposed. The tunable radiated power is achieved by a UWB RF buffer with a peak value controller. The designed low-complex narrow pulse generator and digital ring on–off VCO ensure a high speed transmitting. The low power is realized by using a subtractor to eliminate the base-band component from the output of the VCO and making the UWB RF buffer and the VCO operating in standby mode. The design was fabricated by a standard 0.18μm CMOS technology. The test results show that the design can achieve maximum data-rate of 250Mbps, frequency bandwidth from 3 to 5GHz, radiated power tuning from −40dBm to −60dBm, low-power of 8pJ/bit, and small circuit area of 0.18mm2.