Subleq $_\circleddash$ : An Area-Efficient Two-Instruction-Set Computer

Abstract

Applications with strict resource/power constraints demand the research and development of area-efficient processor designs that deliver reasonably good performance with small circuit area. While the ARM and RISC-V instruction set architecture (ISAs) are lightweight alternatives to $\boldsymbol \times 86$ , they nevertheless consume considerable circuit area and power. In this letter, we return to a fundamental question: how area efficient can a processor be while retaining the property of being “turing complete” (i.e., capable of realizing any computation)? Beginning with a recently published one-instruction-set computer, that uses a minimal amount of resources, we consider adding a second instruction to the instruction set and justify the choice of such an instruction. An experimental study illustrates the benefits of our ISA extension in terms of performance at minimal area cost.