Abstract
Energy-efficient timer circuits are required in numerous applications for periodic operations, such as performing measurements and communicating data. In this paper, we present a gate-leakage-based timer that utilizes an amplifier-less replica-bias switching technique to generate a stable frequency, which can operate at a low supply voltage. To guarantee a stable oscillation frequency in a small circuit area, the proposed design adopts an architecture that discharges a pre-charged capacitor through a resistive element (gate-leaking MOS capacitor) with a low-leakage switch. In the proposed switching technique, the low-voltage timer operates by tracking the discharging terminal of the capacitor and biasing the reference voltage of the switch unit, thereby enabling the minimization of the leakage current without the need for analog amplifier circuits. The high supply sensitivity of the timer is addressed by regulating the supply voltage using a native NMOS header (NNH). The proposed design is fabricated using the 55-nm deeply depleted channel (DDC) CMOS technology, which has a strong body coefficient and occupies an active circuit area of 0.0022 mm2. The measurements show that the proposed design can achieve an energy-per-cycle value of 25 pJ/cycle at a supply voltage of 350 mV when body biasing is applied. The measured Allan deviation floor is 200 ppm at room temperature. The timer exhibits an average temperature sensitivity of 810 ppm/°C for four samples. Moreover, a reduction in the supply sensitivity by a factor of 26 using the NNH is demonstrated in an active circuit area of 0.0034 mm2.
Highlights
A TTRACTIVE sensor systems with low-power circuit designs have been developed to address the technical challenge of reducing the size of power sources to achieve further miniaturization and long-term operation [1]
It is a straightforward approach to use wellknown energy sources, such as solar cells, thermoelectric generators, and piezoelectric harvesters, for these sensor systems, important works have explored the possibility of obtaining energy from biological systems [2], [3] that can generate a supply voltage significantly lower than the nominal supply voltages required for the circuit operation of almost all existing CMOS technologies
EXPERIMENTAL RESULTS The test chip of the proposed design was fabricated in 55nm depleted channel (DDC) CMOS technology
Summary
In [8], both the supply and temperature sensitivities of the gate-leakage-based timer were significantly reduced by employing a frequency-locked architecture and low-power reference circuits without sacrificing energy efficiency. These designs require a multi-supply voltage topology or analog circuits, namely amplifiers, charge pumps, and comparators. As a result, it may be difficult for the aforementioned approaches to achieve efficient performance while operating in the deep subthreshold region.
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