Session 8 Overview: Circuits for Digital Systems

Abstract

As clock frequencies push towards 10GHz, new circuit techniques are needed to meet the aggressive cycle times demanded for these next-generation systems. At the same time, noise and power issues also drive the need for innovative circuit techniques, since excessive noise or power compromises the ultimate operating frequency of the system. The papers in this session describe approaches to attack these challenges, with two papers presenting ultra-high frequency circuit designs, another paper featuring a style of self-timed operation, and a fourth paper introducing an active noise suppression scheme. In addition, three papers describe special low power or low voltage techniques. In Paper 8.1, self-timed techniques are used for the implementation of a priority queue. This circuit operates in a bucket relay fashion, whereby arriving packets are queued and scheduled autonomously in a self-timed manner. Self-timed circuits are expected to offer advantages in terms of lower power operation, scalability, and robustness. Demonstrating the concept of an Internet network on a chip, Paper 8.2 presents a wide bandwidth interconnection network optimized for low power implementation of portable multimedia SoC. This network allows integration of heterogeneous cores and functional blocks operating at independent frequencies. A low energy transmission encoding scheme delivers high bandwidth with low power consumption. Paper 8.3 describes a family of high performance low-voltage-swing NMOS logic circuits, coupled with PMOS sense amplifiers, allowing operation at frequencies approaching 7GHz in an x86 integer core. Fast MUX, adder, rotator and shifter circuits take advantage of the depth of logic offered by this circuit family, running at twice the processor core clock frequency. Body biasing techniques are described in the next two papers, with the goal of improving operation at low supply voltages or minimizing performance variability. In Paper 8.4, PMOS and NMOS body biases are swapped in order to increase the operating frequency and power efficiency at very low supply voltages. These design techniques allow a larger operating supply voltage range with flexible threshold voltage combinations for better energy efficiency at supply voltages below 500mV. The second paper on body biasing schemes, Paper 8.5 presents a sophisticated body bias technique which allows designers to choose between feedback mechanisms either designed to hold the threshold voltage constant, or hold saturation current constant, depending on the circuit sensitivities. This allows a reduction in delay variations, and also an improvement in overall power consumption of CMOS logic and memory circuits. Next in the session, Paper 8.6 attacks crosstalk noise problems in twin-well CMOS designs, expected to be a significant problem in GHz SoCs. Op-amp active decoupling circuits are built using Miller capacitance multiplication to suppress substrate noise over a wide frequency range. This solves the parasitic inductance problems encountered by more conventional active decoupling schemes in wireless applications. Paper 8.7 describes a multimode ALU, operating at frequencies up to 7GHz in 32b mode, and up to 4GHz in 64b mode in 90nm dual-VT CMOS technology. The ALU relies on single-rail dynamic circuits and a sparse-tree semidynamic adder to improve the performance, reduce the area, and lower the energy consumption. Usage of a dualVT CMOS process allows high noise robustness without sacrificing high speed operation.