Small Amount Of Memory Research Articles

Fibonacci and Galois representations of feedback-with-carry shift registers

A feedback-with-carry shift register (FCSR) with architecture is a shift register provided with a small amount of memory which is used in the feedback algorithm. Like the linear feedback shift register (LFSR), the FCSR provides a simple and predictable method for the fast generation of pseudorandom sequences with good statistical properties and large periods. In this paper, we describe and analyze an alternative architecture for the FCSR which is similar to the architecture for the LFSR. The Galois architecture is more efficient than the Fibonacci architecture because the feedback computations are performed in parallel. We also describe the output sequences generated by the d-FCSR, a slight modification of the (Fibonacci) FCSR architecture in which the feedback bit is delayed for d clock cycles before being returned to the first cell of the shift register. We explain how these devices may be configured so as to generate sequences with large periods. We show that the d-FCSR also admits a more efficient architecture.

Squeezer: An efficient algorithm for clustering categorical data

This paper presents a new efficient algorithm for clustering categorical data, Squeezer, which can produce high quality clustering results and at the same time deserve good scalability. The Squeezer algorithm reads each tuple t in sequence, either assigning t to an existing cluster (initially none), or creating t as a new cluster, which is determined by the similarities between t and clusters. Due to its characteristics, the proposed algorithm is extremely suitable for clustering data streams, where given a sequence of points, the objective is to maintain consistently good clustering of the sequence so far, using a small amount of memory and time. Outliers can also be handled efficiently and directly in Squeezer. Experimental results on real-life and synthetic datasets verify the superiority of Squeezer.

New directions in traffic measurement and accounting

Accurate network traffic measurement is required for accounting, bandwidth provisioning and detecting DoS attacks. These applications see the traffic as a collection of flows they need to measure. As link speeds and the number of flows increase, keeping a counter for each flow is too expensive (using SRAM) or slow (using DRAM). The current state-of-the-art methods (Cisco's sampled NetFlow) which log periodically sampled packets are slow, inaccurate and resource-intensive. Previous work showed that at different granularities a small number of "heavy hitters" accounts for a large share of traffic. Our paper introduces a paradigm shift for measurement by concentrating only on large flows --- those above some threshold such as 0.1% of the link capacity.We propose two novel and scalable algorithms for identifying the large flows: sample and hold and multistage filters, which take a constant number of memory references per packet and use a small amount of memory. If $M$ is the available memory, we show analytically that the errors of our new algorithms are proportional to $1/M$; by contrast, the error of an algorithm based on classical sampling is proportional to $1/\sqrtM$, thus providing much less accuracy for the same amount of memory. We also describe further optimizations such as early removal and conservative update that further improve the accuracy of our algorithms, as measured on real traffic traces, by an order of magnitude. Our schemes allow a new form of accounting called threshold accounting in which only flows above a threshold are charged by usage while the rest are charged a fixed fee. Threshold accounting generalizes usage-based and duration based pricing.

Registration of Multiple Acoustic Range Views for Underwater Scene Reconstruction

This paper proposes a technique for the three-dimensional reconstruction of an underwater environment from multiple acoustic range views acquired by a remotely operated vehicle. The problem is made challenging by the very noisy nature of the data, the low resolution, and the narrow field of view. Our main contribution is a new global registration technique to distribute registration errors evenly across all views. Our approach does not use data points after the first pairwise registration, for it works only on the transformations. Therefore, it is fast and occupies only a small amount of memory. Experimental results suggest the global registration technique is effective in equalizing the error. Moreover, we introduce a statistically sound thresholding (the X84 rejection rule) to improve ICP robustness against noise and nonoverlapping data.

SVM-based face verification with feature set of small size

An efficient algorithm for face verification is presented, which uses support vector machines with the feature set extracted by genetic algorithms (GA). By using the GA in selecting the discriminating feature set, we obtain a high recognition rate even with a small amount of memory.

SimpleFit: a framework for analyzing design trade-offs in Raw architectures

The semiconductor industry roadmap projects that advances in VLSI technology will permit more than one billion transistors on a chip by the year 2010. The MIT Raw microprocessor is a proposed architecture that strives to exploit these chip-level resources by implementing thousands of tiles, each comprising a processing element and a small amount of memory, coupled by a static two-dimensional interconnect. A compiler partitions fine-grain instruction-level parallelism across the tiles and statically schedules intertile communication over the interconnect. Because Raw microprocessors fully expose their internal hardware structure to the software, they can be viewed as a gigantic FPGA with coarse-grained tiles in which software orchestrates communication over static interconnections. One open challenge in Raw architectures is to determine their optimal grain size and balance. The grain size is the area of each tile and the balance is the proportion of area in each tile devoted to memory, processing, communication, and off-chip global I/O. If the total chip area is fixed, higher processing power per tile requires large tiles and hence reduces the total number of tiles on the chip. This paper presents SimpleFit, a novel analytical framework that designers can use to reason about the design space of Raw microprocessors. Our model is also generalizable to multiprocessors on a chip. Based on an architectural model, an application model, and a VLSI cost analysis, the framework computes the performance of applications and uses an optimization process to identify designs that will execute these applications most cost-effectively, Although the optimal machine configurations obtained vary for different applications, problem sizes, and budgets, the general trends for various applications are similar. Accordingly, for the applications studied, assuming a one billion logic transistor equivalent area, we recommend building a Raw chip with approximately 1,000 tiles, 30 words/cycle global I/O, 20 Kbytes of local memory per tile, three to four words/cycle local communication bandwidth, and single-issue processors. This configuration will give performance near the global optimum for most applications.

Minimax real-time heuristic search

Real-time heuristic search methods interleave planning and plan executions and plan only in the part of the domain around the current state of the agents. So far, real-time heuristic search methods have mostly been applied to deterministic planning tasks. In this article, we argue that real-time heuristic search methods can efficiently solve nondeterministic planning tasks. We introduce Min-Max Learning Real-Time A∗ (Min-Max LRTA∗), a real-time heuristic search method that generalizes Korf's LRTA∗ to nondeterministic domains, and apply it to robot-navigation tasks in mazes, where the robots know the maze but do not know their initial position and orientation (pose). These planning tasks can be modeled as planning tasks in nondeterministic domains whose states are sets of poses. We show that Min-Max LRTA∗ solves the robot-navigation tasks fast, converges quickly, and requires only a small amount of memory.

Orientation lightmaps for photon tracing in complex environments

We present a method that makes the use of photon tracing methods feasible for complex scenes when a totally accurate solution is not essential. This is accomplished by using orientation lightmaps, which average the illumination of complex objects depending on the surface normal. Through this averaging, they considerably reduce the variance of the stochastic solution. In order to use these specialised lightmaps, which consume comparatively small amounts of memory, no changes have to be made to the basic photon-tracing algorithm. Also, they can be freely mixed with normal lightmaps. This gives the user good control over the amount of inaccuracy he introduces by their application. The area computations necessary for their insertion are performed using a stochastic sampling method that performs well for highly complex objects.

Efficient real-time correlator for CDMA2000 searcher

A very efficient structure for a real-time searcher in the CDMA2000 system is proposed. The advantages of using this scheme are the small amount of memory required, the processor speed per unit time, and an inherent parallel processing structure. This concept can be applied to other CDMA systems.

A combined input and output queued packet switched system based on PRIZMA switch on a chip technology

A packet-switched system architecture based on the combination of a single-chip output-buffered switch element and input queues that sort arriving packets on a per-output-port basis is proposed. Scheduling is performed in a distributed two-stage approach. Independent arbiters at each of the inputs resolve input contention. Whereas the output-buffered switch element resolves output contention. As a result of this distribution of functionality, complexity of the input arbiters is only linearly proportional to the number of output ports N, thus offering better scalability than purely input-buffered approaches that require complex centralized schedulers. Since the input queues are used as the main buffering mechanism, only a relatively small amount of memory (on the order of N/sup 2/ packet locations) is required in the shared-memory switch, allowing high-throughput implementations. We present simulation results to demonstrate the high performance and robustness under bursty traffic achieved with the proposed system architecture. A practical implementation in the form of the PRIZMA family of switch chips is outlined, with emphasis on its versatility in scaling in terms of both port speed and number of ports, and its support for quality-of-service mechanisms.

Speech processing coder, decoder and command recognizer

The present invention relates to a speech processing device equipped with both a speech coding/decoding function and a speech recognition function, and is aimed at providing a speech processing device equipped with both a speech coding/decoding function and a speech recognition function by using a small amount of memory. The speech processing device of the present invention includes a speech analysis unit for obtaining analysis results by analyzing input speech, a codebook for storing quantization parameters and quantization codes indicating the quantization parameters, a quantizing unit for selecting the quantization parameters and the quantization codes corresponding to the analysis results from the codebook and for outputting selected quantization parameters and selected quantization codes, a coding unit for outputting encoded codes of the input speech including the selected quantization codes, a speech dictionary for storing registered data which represent speech patterns by using the codebook, and a matching unit for obtaining the speech patterns corresponding to the input speech by using one of the analysis results, the selected quantization parameters, and the selected quantization codes.

An efficient document clustering algorithm and its application to a document browser

We present an efficient document clustering algorithm that uses a term frequency vector for each document instead of using a huge proximity matrix. The algorithm has the following features: (1) it requires a relatively small amount of memory and runs fast, (2) it produces a hierarchy in the form of a document classification tree and (3) the hierarchy obtained by the algorithm explicitly reveals a collection structure. We confirm these features and thus show the algorithm's feasibility through clustering experiments in which we use two collections of Japanese documents, the sizes of which are 83,099 and 14,701 documents. We also introduce an application of this algorithm to a document browser. This browser is used in our Japanese-to-English translation aid system. The browsing module of the system consists of a huge database of Japanese news articles and their English translations. The Japanese article collection is clustered into a hierarchy by our method. Since each node in the hierarchy corresponds to a topic in the collection, we can use the hierarchy to directly access articles by topic. A user can learn general translation knowledge of each topic by browsing the Japanese articles and their English translations. We also discuss techniques of presenting a large tree-formed hierarchy on a computer screen.

Auto-associative segmentation for real-time object recognition in realistic outdoor images

As digital signal processors (DSPs) become more advanced, many real-time recognition problems will be solved with completely integrated solutions. In this paper a methodology which is designed for today’s DSP architectures and is capable of addressing applications in real-time color object recognition is presented. The methodology is integrated into a processing structure called raster scan video processing which requires a small amount of memory. The small amount of memory required enables the entire recognition system to be implemented on a single DSP. This auto-associative segmentation approach provides a means for desaturated color images to be segmented. The system is applied to the problem of stop sign recognition in realistically captured outdoor images.

A multiresolution approach for page segmentation

In this work we propose a new page segmentation method for recognizing text and graphics based on a multiresolution representation of the page image. Our approach is based on the analysis of a set of feature maps available at different resolution levels. The final output is a description of the physical structure of a page. A page image is broken down into several blocks which represent components of a page, such as text, line-drawings, and pictures. The result, which uses only a small amount of memory in addition to that for the image, may be the first step for a more detailed analysis such as optical character recognition.

Identification scheme based on quadratic residue

A new interactive identification protocol is presented based on the quadratic residue (QR), which has low computational and communication overheads and only requires a small amount of memory in which to store the secret information. In comparison with another scheme based on the QR, the new scheme achieves the same security level, but is simpler and more efficient.

Diagnostic fault simulation for synchronous sequential circuits

In this paper, a time and memory-efficient diagnostic fault simulator for sequential circuits is first presented. A distributed diagnostic fault simulator is then presented based on the sequential algorithm to improve the speed of the diagnostic process. In the sequential diagnostic fault simulator, the number of fault-pair output response comparisons has been minimized by using an indistinguishability fault list that stores the faults that are indistinguishable from each fault. Due to the symmetrical relationship of the fault-pair distinguishability, fault list sizes are reduced. Therefore, the different diagnostic measures of a given test set can be generated very quickly using a small amount of memory. To further speed up the process of finding the indistinguishable fault list for each fault, a distributed approach is proposed and developed. The major idea for this approach is that each processor constructs the indistinguishable fault lists for a certain percentage of faults only. Experimental results show that the sequential diagnostic fault simulator runs faster and uses less memory than a previously developed one and that the distributed algorithm even achieves superlinear speedup for a very large sequential benchmark circuit, s35932. To the authors' knowledge, no distributed diagnostic fault simulation system for sequential circuits has been proposed before.

The numerical simulation of Gaussian cross-correlated wind velocity fluctuations by means of a hybrid model

Abstract In the present work, a hybrid model is employed to simulate cross-correlated wind velocity components. The model is based on the theory of expansions in convergent series of proper functions of the realizations of the target process, which is the base of parametric models, but the coefficients of the expansion are generated by means of an extended AR filter. The coefficients of the AR filter can be evaluated directly from the spectral density tensor of the target process, without making use of Yule-Walker equations and, consequently, without the integration of the spectral density tensor to find the covariance tensor. In this way, the flexibility of parametric models is retained together with the main characteristics of ARIMA digital filters, which need a relatively small amount of memory in order to generate all the coefficients needed. The goodness of the results is investigated in the frequency domain by means of the comparison between the target and estimated auto- and cross-power spectral densities.

A universal parallel computer architecture

Advances in interconnection network performance and interprocessor interaction mechanisms enable the construction of fine-grain parallel computers in which the nodes are physically small and have a small amount of memory. This class of machines has a much higher ratio of processor to memory area and hence provides greater processor throughput and memory bandwidth per unit cost relative to conventional memory-dominated machines. This paper describes the technology and architecture trends motivating fine-grain architecture and the enabling technologies of high-performance interconnection networks and low-overhead interaction mechanisms. We conclude with a discussion of our experiences with the J-Machine, a prototype fine-grain concurrent computer.

Working sets, cache sizes, and node granularity issues for large-scale multiprocessors

The distribution of resources among processors, memory and caches is a crucial question faced by designers of large-scale parallel machines. If a machine is to solve problems with a certain data set size, should it be built with a large number of processors each with a small amount of memory, or a smaller number of processors each with a large amount of memory? How much cache memory should be provided per processor for cost-effectiveness? And how do these decisions change as larger problems are run on larger machines? In this paper, we explore the above questions based on the characteristics of five important classes of large-scale parallel scientific applications. We first show that all the applications have a hierarchy of well-defined per-processor working sets, whose size, performance impact and scaling characteristics can help determine how large different levels of a multiprocessor's cache hierarchy should be. Then, we use these working sets together with certain other important characteristics of the applications—such as communication to computation ratios, concurrency, and load balancing behavior—to reflect upon the broader question of the granularity of processing nodes in high-performance multiprocessors. We find that very small caches whose sizes do not increase with the problem or machine size are adequate for all but two of the application classes. Even in the two exceptions, the working sets scale quite slowly with problem size, and the cache sizes needed for problems that will be run in the foreseeable future are small. We also find that relatively fine-grained machines, with large numbers of processors and quite small amounts of memory per processor, are appropriate for all the applications.

PC-based system for transparent fluid film monitoring

The detection of impurities in transparent fluid films is an important problem in many industrial applications. An experimental software systems for spurious particle monitoring in flowing transparent fluid films is described. The system operates by building up and maintaining a reference frame against which the actual frame is compared to detect pollution particle. The system itself has been designed with PC-based applications in mind so that only a small amount of memory and a commercial frame grabber suitably interfaced with the PC itself are needed. Adaptive procedures achieve system reliability and flexibility, allowing the system to be introduced in different operating environments with minimal effort.