Slow Clock Research Articles

Power Optimized VLSI Architecture of Distributed Arithmetic Based Block LMS Adaptive Filter

In this paper, we are presenting a power-efficient Distributed Arithmetic (DA) based Block Least Mean Square (BLMS) Adaptive Digital Filter (ADF). The proposed DA BLMS architecture proposes a shared area-efficient Multiplier Accumulate Block that calculates both the partial filter products and the weight increment terms in the same module. It also uses Multiplexers (MUX) and Demultiplexers (DEMUX) which passes only L out of N inputs, where N and L are the filter length and chosen block size respectively, into the MAC thus helping in achieving the DA functionality along with reduced power consumption. Also, efficient truncation of the obtained error and weight update terms is performed by being able to select the non-zero-bit part of the signal to be fed back. The entire architecture is driven by a single slow clock which reduces the power consumption of the device further. On comparing with the best existing DA BLMS Structures, the proposed architecture uses 15% lesser power, 14% lesser EPS according to ASIC Synthesis, and for a filter length of N=16 and a block size of L=4 respectively.

Time perception impairment in multiple sclerosis patients: a survey on internal clock model.

Time perception is known as a mental ability to discern time. Although relative nature of time leaves its numerous aspects undefined, several models have been developed to describe temporal information processing in the brain as well as several areas of the brain have shown to be involved. Time perception alteration has been reported in several neurological conditions; however, the effect of multiple sclerosis (MS) on time perception has yet to be explained. In this study, we aimed to investigate the domains of temporal processing involved in patients with MS and the probable factors affecting it, such as the location of brain demyelinating plaques and gender. Two groups of participants (MS: n = 27 (8 men, 19 women), mean age = 33.85; control: n = 30 (10 men, 20 women), mean age = 28.46) were asked to perform quadruplet time perception tasks (prospective time estimation, duration discrimination, temporal reproduction, and paced motor timing) designed with a software program. Patients with MS had significantly higher scores in time estimation (p < 0.01) and duration discrimination (p < 0.001, in 100-ms interval; p < 0.05, in 1000-ms interval), indicating that MS patients overestimate the time. Since a slower internal clock for MS patients was expected as a result of axonal demyelination, these results suggest the time overestimation in patients with MS which is in contrast with the internal clock model. It means that a slow internal clock causes underestimating and perceiving the time slower.

An Energy-Efficient SIFT Based Feature Extraction Accelerator for High Frame-Rate Video Applications

Visual feature extraction is a key technology of computer vision for intelligent video processing. Efficient feature extraction is a fundamental problem in computer vision applications. Scale-Invariant Feature Transform (SIFT) is one of the most popular feature extraction algorithms because SIFT features are invariant to image scale and rotation and robust to changes in illumination and noise. However, SIFT is a computationally-intensive and power-hungry algorithm, which needs to be accelerated by efficient hardware design to achieve both high-speed feature extraction and high energy efficiency for many high frame-rate video applications at Artificial-intelligent Internet of Things edges. In this work, an energy-efficient SIFT based feature extraction accelerator is proposed. In the Gaussian pyramid and Differences of Gaussian (DoG) pyramid construction process, three design methods are proposed to reduce power consumption and improve information fidelity: a fast and slow dual clock domain design method with a reconfigurable design strategy is proposed to reduce the computation resources; a partial sum reuse design method is proposed to further reduce the computation resources and the amount of computation; a dynamic padding design method is proposed to solve the problem of information loss at image edges and corners after convolution operation. In the keypoint descriptor generation process, an optimized algorithm using circular region and polar coordinates is proposed to parallelize the main orientation assignment and descriptor generation to achieve high-speed processing, while maintaining a comparable matching accuracy with the state-of-the-art designs. The experiment results show that the proposed SIFT hardware accelerator is able to extract features by up to 162 frames per second ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$640\times 480$ </tex-math></inline-formula> pixels) under 100 MHz, with the power consumption of 364.26 mW and energy efficiency of 2.25 mJ/frame based on 180 nm technology, which is suitable for many high frame-rate AIoT applications including autonomous driving cars and unmanned aerial vehicles.

Massive object velocity method for clock synchronization

A clock synchronization method is presented based on temporal calibration obtained via the propagation of a massive object. The calibrated massive object velocity combined with launch and receive synchronizations allows synchronization of a distal clock. This approach is an alternative to classical electromagnetic synchronization methods and the slow clock transport concept. The method is presented as an analog to electromagnetic clock synchronization. Relativistic effects and local synchronization between the object and clock are discussed.

Low Power ALU using Wave Shaping Diode Adiabatic Logic

The evolution of portable electronic devices and their widespread application has led to an increased focus on power dissipation as one of the critical parameters. An increase in functionality requirement and design complexity on a single chip has resulted in increased power dissipation. High power dissipation has motivated study and innovation on low power circuit design techniques. Adiabatic logic has been studied as one of the design techniques to reduce power dissipation by reusing the power that was getting dissipated in conventional designs. This paper presents the application of Wave Shaping Diode Adiabatic Logic (WSDAL) to implement an ALU and analyse the improvement in power dissipation as compared to the conventional CMOS design. The WSDAL design uses a slow and time-fluctuating 2-phase sinusoidal Power Clock (PC), which supplies power as well as a clock to the designs. WSDAL uses an Ultra-Low Power Diode (ULPD) structure that operates as a wave shaping device and reduces glitches at the output. The design has been implemented in OrCAD Capture and simulated using Pspice in TSMC 180nm technology. The simulations were performed at 200MHz PC frequency and power dissipation was studied over a range of voltages from 1.4V to 2.2V. The simulations show that WSDAL ALU dissipates less power than the CMOS design. This study indicates that WSDAL-based designs have the potential to be deployed for power dissipation reduction in portable devices.

FPGA Accelerator for Real-Time Non-Line-of-Sight Imaging

Non-line-of-sight (NLOS) imaging systems reconstruct hidden scenes using computational methods based on indirect light that diffusely reflected from relay walls. Due to the computation and memory requirements of reconstruction algorithms, real-time NLOS imaging for room-size scenes based on non-confocal data has long been challenging. This paper proposes a field programmable gate array (FPGA) accelerator for the recently proposed Rayleigh-Sommerfeld Diffraction (RSD)-based NLOS reconstruction method. In the proposed accelerator design, ring sampling and radius sampling techniques are proposed to reduce the memory requirements by reconstructing the RSD kernels with a set of kernel bases and ring sampling coefficients during the runtime. Based on that, a customized hardware architecture and the corresponding FPGA design for real-time RSD-based NLOS reconstruction is further proposed. Implementation results show that the proposed FPGA accelerator is capable of reconstructing NLOS scenes at 25 frames per second (FPS), running at a relatively slow clock frequency of 50 MHz. To the best knowledge of the authors, this is the first real-time enabled FPGA accelerator for room-size NLOS imaging with a resolution of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$128\times 128$ </tex-math></inline-formula> .

Switched-Capacitor Bandgap Voltage Reference for IoT Applications

This paper presents a switched-capacitor network (SCN) based bandgap voltage reference (BGR) for IoT applications. The proposed BGR employs a dual proportional-to-absolute-temperature (PTAT) clock topology to achieve both high precision and low power over a wide temperature range while relaxing the capacitor size requirements. Specifically, the fast PTAT clock assists in reducing the output voltage ripple of the dual-branch interleaved <inline-formula> <tex-math notation="LaTeX">$2\times $ </tex-math></inline-formula> charge pump (CP). Meanwhile, the slow PTAT clock controls the voltage divider SCN to relax the settling error at low temperature and the leakage-induced error at high temperature simultaneously, resulting in lower power consumption and smaller temperature coefficient (TC). We also propose a replica <inline-formula> <tex-math notation="LaTeX">$V_{\mathrm {EB}}$ </tex-math></inline-formula> generation branch in the series-parallel SCN to improve the BGR output TC due to the finite settling time during switching. Fabricated in 65nm standard CMOS, measurement results show that the proposed BGR obtains a TC of 32 ppm/&#x00B0;C at 0.5V supply within &#x2212;40 &#x00B0;C to 120 &#x00B0;C. The line regulation is 3.3mV/V or 0.66&#x0025;/V from 0.5V to 1V. Based on 10-chip measurement results, we obtain a <inline-formula> <tex-math notation="LaTeX">$3\sigma / \mu $ </tex-math></inline-formula> variation of 1.37&#x0025; before trimming, while 0.25&#x0025; after applying one-point trimming at 20&#x00B0;C.

Reversible Fluxon Logic With Optimized CNOT Gate Components

Reversible logic gates were previously implemented in superconducting circuits as adiabatic-reversible gates, which are powered with a sufficiently slow clock. In contrast, we are studying ballistic-reversible gates, where fluxons serve to both encode the information and power the gates. No power is applied to the gate apart from the energy of the input fluxons, and the two possible flux polarities represent the bit states. Undamped long Josephson junctions (LJJs), where fluxons move at practically constant speed from inertia, form the input and output channels of the gates. LJJs are connected in the gates by circuit interfaces, which are designed to allow the ballistic scattering from input to output fluxon states, using the temporary excitation of a localized mode. The duration of the resonant scattering determines the operation time of the gate, approximately a few Josephson plasma periods. Due to the coherent conversions between fluxon and localized modes the ballistic gates can be very efficient: in our simulations only a few percent of the fluxon's energy are dissipated in the gate operation. Ballistic-reversible gates can be combined with other, non-ballistic gate circuits to extend the range of gate functionalities. Here we describe how the CNOT can be built as a structure that includes the IDSN (Identity-else-Same-gives-NOT) and Store-and-Launch (SNL) gates. The IDSN is a 2-bit ballistic gate, which we describe and analyze in terms of equivalent 1-bit circuits. The SNL is a clocking gate, that allows the storage of a bit and the clocked launch of a fluxon on a bit-state dependent output path. In the CNOT the SNL gates provide the necessary routing and fluxon synchronization for the input to the IDSN gate.

Boosting working memory with accelerated clocks

Our perception of time varies with the degree of cognitive engagement in tasks. The perceived passage of time accelerates while working on demanding tasks, whereas time appears to drag during boring situations. Our experiment aimed at investigating whether this relationship is mutual: Can manipulated announcements of elapsed time systematically affect the attentional resources applied to a cognitive task? We measured behavioral performance and the EEG in a whole report working memory paradigm with six items of different colors that each had to be reported after a short delay period. The 32 participants were informed about the current time after each 20 trials, while the clock was running at either 100% (normal), 120% (fast), or 80% (slow) of normal clock speed depending on the experimental block. The mean number of correctly reported colors per trial was significantly increased in the fast as compared to the slow and normal clock conditions. In the EEG, we focused on neural oscillations during working memory encoding and storage. As an electrophysiological correlate of task engagement, frontal theta power during the storage interval was increased in the fast clock condition. Also, the power of frontal theta oscillations predicted the number of correctly reported colors on a single-trial basis. This shows that a covert manipulation of clock speed can lead to an improvement in cognitive performance, presumably mediated by a higher allocation of attentional resources resulting from an adaptation of the subjective passage of time during an experiment.

Depth-bounded Graph Partitioning Algorithm and Dual Clocking Method for Realization of Superconducting SFQ Circuits

Superconducting Single Flux Quantum (SFQ) logic with switching delay of 1ps and switching energy of 10 −19 J is a potential emerging candidate for replacing Complementary Metal Oxide Semiconductor (CMOS) to achieve very high speed and ultra energy efficiency. Conventional SFQ circuits need Full Path Balancing (FPB), which tends to require insertion of many path balancing buffers (D-Flip-Flops). FPB method increases total power consumption as well as total area of the chip. This article presents a novel scheme for realization of superconducting SFQ circuits by introducing a new depth-bounded graph partitioning algorithm in combination with a dual clocking method (slow and fast clock pulses) that minimizes the aforesaid path balancing overheads. Experimental results show that the proposed solution reduces total number of path balancing buffers and total static power consumption by an average of 2.68× and 60%, respectively, when compared to the best of other methods for realizing SFQ circuits. However, our scheme degrades the peak throughput; therefore, it is especially valuable when the actual throughput of the SFQ circuit is much lower than the peak theoretical throughput. This is typically the case due to high-level data dependencies of the application that feeds data into an SFQ circuit.

Pulse Width Insensitive Design and Verification Methods

Many embedded controllers have some critical system states that depend on an asynchronous event. Currently handling them in design depends on the availability of always-on slow clocks. In this paper we present a generic asynchronous design scheme that doesn't require a clock and ensure a reliable functionality without associated deadlock scenarios sensitive to exact arrival times of asynchronous events. This is enabled by a novel pulse width insensitive design method, which also requires unconventional verification methodology that ensures thorough and comprehensive pre-silicon design quality. These have been applied on the latest, ultra-low cost embedded micro-controller design targeted for cost sensitive applications.

Amplitude Effects Allow Short Jet Lags and Large Seasonal Phase Shifts in Minimal Clock Models

Mathematical models of varying complexity have helped shed light on different aspects of circadian clock function. In this work, we question whether minimal clock models (Goodwin models) are sufficient to reproduce essential phenotypes of the clock: a small phase response curve (PRC), fast jet lag, and seasonal phase shifts. Instead of building a single best model, we take an approach where we study the properties of a set of models satisfying certain constraints; here, a 1h-pulse PRC with a range of 3h and clock periods between 22h and 26h is designed. Surprisingly, almost all these randomly parameterized models showed a 4h change in phase of entrainment between long and short days and jet lag durations of three to seven days in advance and delay. Moreover, intrinsic clock period influenced jet lag duration and entrainment amplitude and phase. Fast jet lag was realized in this model by means of an interesting amplitude effect: the association between clock amplitude and clock period termed “twist.” This twist allows amplitude changes to speed up and slow down clocks enabling faster shifts. These findings were robust to the addition of positive feedback to the model. In summary, the known design principles of rhythm generation – negative feedback, long delay, and switch-like inhibition (we review these in detail) – are sufficient to reproduce the essential clock phenotypes. Furthermore, amplitudes play a role in determining clock properties and must be always considered, although they are difficult to measure.

New Drosophila Circadian Clock Mutants Affecting Temperature Compensation Induced by Targeted Mutagenesis of Timeless.

Drosophila melanogaster has served as an excellent genetic model to decipher the molecular basis of the circadian clock. Two key proteins, PERIOD (PER) and TIMELESS (TIM), are particularly well explored and a number of various arrhythmic, slow, and fast clock mutants have been identified in classical genetic screens. Interestingly, the free running period (tau, τ) is influenced by temperature in some of these mutants, whereas τ is temperature-independent in other mutant lines as in wild-type flies. This, so-called “temperature compensation” ability is compromised in the mutant timeless allele “ritsu” (timrit), and, as we show here, also in the timblind allele, mapping to the same region of TIM. To test if this region of TIM is indeed important for temperature compensation, we generated a collection of new mutants and mapped functional protein domains involved in the regulation of τ and in general clock function. We developed a protocol for targeted mutagenesis of specific gene regions utilizing the CRISPR/Cas9 technology, followed by behavioral screening. In this pilot study, we identified 20 new timeless mutant alleles with various impairments of temperature compensation. Molecular characterization revealed that the mutations included short in-frame insertions, deletions, or substitutions of a few amino acids resulting from the non-homologous end joining repair process. Our protocol is a fast and cost-efficient systematic approach for functional analysis of protein-coding genes and promoter analysis in vivo. Interestingly, several mutations with a strong temperature compensation defect map to one specific region of TIM. Although the exact mechanism of how these mutations affect TIM function is as yet unknown, our in silico analysis suggests they affect a putative nuclear export signal (NES) and phosphorylation sites of TIM. Immunostaining for PER was performed on two TIM mutants that display longer τ at 25°C and complete arrhythmicity at 28°C. Consistently with the behavioral phenotype, PER immunoreactivity was reduced in circadian clock neurons of flies exposed to elevated temperatures.

Analysis, Calibration, and Performance Evaluation of a Generalized &lt;inline-formula&gt; &lt;tex-math notation="LaTeX"&gt;$N$ &lt;/tex-math&gt; &lt;/inline-formula&gt;-Phase Quadrature Phase Shift Frequency Selective Receiver

In this paper, a new low-power and blocker-tolerant receiver architecture, the generalized N-phase quadrature phase shift frequency selective (QPS-FS), is proposed and analyzed that is suitable for radio frequency (RF) energy harvesting networks. A complete comparative analysis of the N-phase QPS-FS receiver with conventional N-path passive mixer (P-M) receiver is also provided. The QPS-FS receiver utilizes the impedance translation concept to improve the receiver selectivity but eliminates the need of an active multiphase clock generation circuit used in the conventional N-path P-M receivers. It uses a single clock signal source at the desired signal carrier frequency and a phase shift network in the RF path of the receiver for frequency downconversion and quadrature (I/Q) demodulation. The QPS-FS receiver requires a slower clock signal source, the frequency of which is equal to the desired band RF signal carrier frequency ( $f_{c})$ as opposed to at least N/2 times $f_{c}$ for the conventional N-path P-M receivers. Consequently, the lower frequency clock source requirement extends the frequency coverage of the receiver by a factor of at least N/2 for a given clock source with a fixed maximum frequency. Reduction of the operating frequency and elimination of the active multiphase clock generation circuit would also eventually reduce the overall power consumption for the whole receiver system as confirmed through measurements. A wideband receiver calibration approach provides less than 2% of error vector magnitudes between the transmitted and received constellation points for various modulated signals having bandwidths up to 4 MHz.

DDRNoC

This article introduces DDRNoC, an on-chip interconnection network capable of routing packets at Dual Data Rate. The cycle time of current 2D-mesh Network-on-Chip routers is limited by their control as opposed to the datapath (switch and link traversal), which exhibits significant slack. DDRNoC capitalizes on this observation, allowing two flits per cycle to share the same datapath. Thereby, DDRNoC achieves higher throughput than a Single Data Rate (SDR) network. Alternatively, using lower voltage circuits, the above slack can be exploited to reduce power consumption while matching the SDR network throughput. In addition, DDRNoC exhibits reduced clock distribution power, improving energy efficiency, as it needs a slower clock than a SDR network that routes packets at the same rate. Post place and route results in 28nm technology show that, compared to an iso-voltage (1.1V) SDR network, DDRNoC improves throughput proportionally to the SDR datapath slack. Moreover, a low-voltage (0.95V) DDRNoC implementation converts that slack to power reduction offering the 1.1V SDR throughput at a substantially lower energy cost.

A 67.1-ps FOM, 0.5-V-Hybrid Digital LDO With Asynchronous Feedforward Control Via Slope Detection and Synchronous PI With State-Based Hysteresis Clock Switching

We present a fully integrated digital low-drop-out regulator (LDO) with a 100-pF output capacitor ( ${C} _{\textbf {OUT}}$ ) in 65 nm, based on hybrid-synchronous-asynchronous control. The goal is to minimize both response and settling time for abrupt load changes, which in turn enables the ${C} _{\textbf {OUT}}$ scaling under a voltage droop constraint. The architecture is based on the synchronous proportional-integral feedback control in tandem with the asynchronous feedforward control. The asynchronous control loop employs load-event-based triggering , which compensates the output voltage immediately after a voltage droop, shortening response time. Then, the synchronous loop operates on either fast or slow clock selected automatically by a hysteresis control and quickly brings the output to the steady state, achieving short settling time. The proposed hysteresis control achieves superior stability and scales the lower bound of the slow-clock frequency by two orders over the existing scheme. The LDO prototype improves the response- and settling-time related metrics over the prior synchronous and asynchronous LDOs.

The effects of self-selected light-dark cycles and social constraints on human sleep and circadian timing: a modeling approach

Why do we go to sleep late and struggle to wake up on time? Historically, light-dark cycles were dictated by the solar day, but now humans can extend light exposure by switching on artificial lights. We use a mathematical model incorporating effects of light, circadian rhythmicity and sleep homeostasis to provide a quantitative theoretical framework to understand effects of modern patterns of light consumption on the human circadian system. The model shows that without artificial light humans wakeup at dawn. Artificial light delays circadian rhythmicity and preferred sleep timing and compromises synchronisation to the solar day when wake-times are not enforced. When wake-times are enforced by social constraints, such as work or school, artificial light induces a mismatch between sleep timing and circadian rhythmicity (‘social jet-lag’). The model implies that developmental changes in sleep homeostasis and circadian amplitude make adolescents particularly sensitive to effects of light consumption. The model predicts that ameliorating social jet-lag is more effectively achieved by reducing evening light consumption than by delaying social constraints, particularly in individuals with slow circadian clocks or when imposed wake-times occur after sunrise. These theory-informed predictions may aid design of interventions to prevent and treat circadian rhythm-sleep disorders and social jet-lag.

Deep-pipelined FPGA Implementation of Real-time Object Tracking using a Particle Filter

This paper presents a real-time FPGA implementation of the posterior system state estimation in dynamic models, which is developed using particle filter algorithm. Specially, our system is constructed by parallel resampling (FO-resampling) algorithm on a stream-based architecture. To be precise, the resampling is accomplished in a valid pixel area of an input image frame while prediction and update of particles are performed in a synchronization region, thus our approach achieves realtime performance of 60 fps for VGA images, synchronized with the camera pixel throughput without using any external memory devices. Through evaluation with an object tracking benchmark video, the tradeoff relationship between tracking quality and the number of particles is analyzed to find an appropriate hardware parameters. In addition, we address improvement of resource utilization for our particle filter architecture, especially by using a higher clock frequency to reuse hardware resources in a time sharing manner. The implementation experiments reveal that the proposed approach allows the original design to be fitted in a smaller FPGA chip. However, we also demonstrate this size reduction approach has an overhead of 2.7 to 3.0 times power consumption compared to original designs with a slow clock frequency.

RQNoC

In this article, we describe RQNoC, a service-oriented Network-on-Chip (NoC) resilient to permanent faults. We characterize the network resources based on the particular service that they support and, when faulty, bypass them, allowing the respective traffic class to be redirected. We propose two alternatives for service redirection, each having different advantages and disadvantages. The first one, Service Detour, uses longer alternative paths through resources of the same service to bypass faulty network parts, keeping traffic classes isolated. The second approach, Service Merge, uses resources of other services providing shorter paths but allowing traffic classes to interfere with each other. The remaining network resources that are common for all services employ additional mechanisms for tolerating faults. Links tolerate faults using additional spare wires combined with a flit-shifting mechanism, and the router control is protected with Triple-Modular-Redundancy (TMR). The proposed RQNoC network designs are implemented in 65nm technology and evaluated in terms of performance, area, power consumption, and fault tolerance. Service Detour requires 9% more area and consumes 7.3% more power compared to a baseline network, not tolerant to faults. Its packet latency and throughput is close to the fault-free performance at low-fault densities, but fault tolerance and performance drop substantially for 8 or more network faults. Service Merge requires 22% more area and 27% more power than the baseline and has a 9% slower clock. Compared to a fault-free network, a Service Merge RQNoC with up to 32 faults has increased packet latency up to 1.5 to 2.4× and reduced throughput to 70% or 50%. However, it delivers substantially better fault tolerance, having a mean network connectivity above 90% even with 32 network faults versus 41% of a Service Detour network. Combining Serve Merge and Service Detour improves fault tolerance, further sustaining a higher number of network faults and reduced packet latency.

Embedded network camera processor system on a chip for various low-power multimedia applications

In this paper we present an embedded network camera processor (NCP) system on a chip (SoC) for various low-power multimedia applications. The NCP SoC comprises a digital camera processor optimized for a CCD sensor, a motion JPEG encoder to compress the data, an Ethernet controller to transmit the data, ARM processor and many peripherals. Using the NCP SoC allows the raw image from a CCD sensor to be filtered, compressed and transmitted anywhere through various Ethernet protocols, with no additional hardware. The NCP SoC is designed with Verilog-HDL. Also, we followed a strict ASIC flow including functional behavior verification and a scan test. The NCP SoC is fabricated with 0.25 $${\upmu }{\text {m}}$$μm CMOS technology. The total chip size, including embedded memory, is $$7800\times 7800\,{\upmu }{\text {m}}^{2}$$7800×7800μm2 and the gate count is 1.2 million. The NCP SoC runs at up to 48 MHz, and supports various slower clock frequencies for low-power applications requiring additional power saving modes: 6 MHs, 12 and 24 MHz at 2.5 V.