Power Optimized VLSI Architecture of Distributed Arithmetic Based Block LMS Adaptive Filter

Abstract

In this paper, we are presenting a power-efficient Distributed Arithmetic (DA) based Block Least Mean Square (BLMS) Adaptive Digital Filter (ADF). The proposed DA BLMS architecture proposes a shared area-efficient Multiplier Accumulate Block that calculates both the partial filter products and the weight increment terms in the same module. It also uses Multiplexers (MUX) and Demultiplexers (DEMUX) which passes only L out of N inputs, where N and L are the filter length and chosen block size respectively, into the MAC thus helping in achieving the DA functionality along with reduced power consumption. Also, efficient truncation of the obtained error and weight update terms is performed by being able to select the non-zero-bit part of the signal to be fed back. The entire architecture is driven by a single slow clock which reduces the power consumption of the device further. On comparing with the best existing DA BLMS Structures, the proposed architecture uses 15% lesser power, 14% lesser EPS according to ASIC Synthesis, and for a filter length of N=16 and a block size of L=4 respectively.