Abstract
Many embedded controllers have some critical system states that depend on an asynchronous event. Currently handling them in design depends on the availability of always-on slow clocks. In this paper we present a generic asynchronous design scheme that doesn't require a clock and ensure a reliable functionality without associated deadlock scenarios sensitive to exact arrival times of asynchronous events. This is enabled by a novel pulse width insensitive design method, which also requires unconventional verification methodology that ensures thorough and comprehensive pre-silicon design quality. These have been applied on the latest, ultra-low cost embedded micro-controller design targeted for cost sensitive applications.
Highlights
Explosion of portable, battery operated, autonomous embedded internet-of-things (IOT) market and related application require low power and low cost as the DNA for all underlying building blocks
Though in an ideal system the transition between S-1 and S-2 is considered seamless, in an actual clock-less implementation with delay elements, there is a finite time window during the state transition that is in a pseudo-state
The cells used in the delay elements or glitch gobbler circuits are not characterised for pulse width filtering characteristic
Summary
Battery operated, autonomous embedded internet-of-things (IOT) market and related application require low power and low cost as the DNA for all underlying building blocks. The cells used in the delay elements or glitch gobbler circuits are not characterised for pulse width filtering characteristic This mandates a EAI Endorsed Transactions on costlier SPICE based simulation at system level to verify the robustness of the design. In this paper we propose a novel pulse width insensitive asynchronous design method that doesn’t use any flip-flop or edge sensitive circuit elements. This scheme utilizes inherent glitch filtering behaviour of combinatorial gates. There is no automated gate-level tools/methodology available to design, synthesize or verify such designs To overcome this challenge we propose a pulse width sensitive analysis capability for gate level simulation to avoid SPICE based simulations at system level.
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