A 67.1-ps FOM, 0.5-V-Hybrid Digital LDO With Asynchronous Feedforward Control Via Slope Detection and Synchronous PI With State-Based Hysteresis Clock Switching

Abstract

We present a fully integrated digital low-drop-out regulator (LDO) with a 100-pF output capacitor ( ${C} _{\textbf {OUT}}$ ) in 65 nm, based on hybrid-synchronous-asynchronous control. The goal is to minimize both response and settling time for abrupt load changes, which in turn enables the ${C} _{\textbf {OUT}}$ scaling under a voltage droop constraint. The architecture is based on the synchronous proportional-integral feedback control in tandem with the asynchronous feedforward control. The asynchronous control loop employs load-event-based triggering , which compensates the output voltage immediately after a voltage droop, shortening response time. Then, the synchronous loop operates on either fast or slow clock selected automatically by a hysteresis control and quickly brings the output to the steady state, achieving short settling time. The proposed hysteresis control achieves superior stability and scales the lower bound of the slow-clock frequency by two orders over the existing scheme. The LDO prototype improves the response- and settling-time related metrics over the prior synchronous and asynchronous LDOs.