Slew Rate Research Articles

Stochastic optimization of three-dimensional non-Cartesian sampling trajectory.

Optimizing three-dimensional (3D) k-space sampling trajectories is important for efficient MRI yet presents a challenging computational problem. This work proposes a generalized framework for optimizing 3D non-Cartesian sampling patterns via data-driven optimization. We built a differentiable simulation model to enable gradient-based methods for sampling trajectory optimization. The algorithm can simultaneously optimize multiple properties of sampling patterns, including image quality, hardware constraints (maximum slew rate and gradient strength), reduced peripheral nerve stimulation (PNS), and parameter-weighted contrast. The proposed method can either optimize the gradient waveform (spline-based freeform optimization) or optimize properties of given sampling trajectories (such as the rotation angle of radial trajectories). Notably, the method can optimize sampling trajectories synergistically with either model-based or learning-based reconstruction methods. We proposed several strategies to alleviate the severe nonconvexity and huge computation demand posed by the large scale. The corresponding code is available as an open-source toolbox. We applied the optimized trajectory to multiple applications including structural and functional imaging. In the simulation studies, the image quality of a 3D kooshball trajectory was improved from 0.29 to 0.22 (NRMSE) with Stochastic optimization framework for 3D NOn-Cartesian samPling trajectorY (SNOPY) optimization. In the prospective studies, by optimizing the rotation angles of a stack-of-stars (SOS) trajectory, SNOPY reduced the NRMSE of reconstructed images from 1.19 to 0.97 compared to the best empirical method (RSOS-GR). Optimizing the gradient waveform of a rotational EPI trajectory improved participants' rating of the PNS from "strong" to "mild." SNOPY provides an efficient data-driven and optimization-based method to tailor non-Cartesian sampling trajectories.

An 18-bit 2-2 MASH delta-sigma modulator for isolated amplifier

This paper presents an 18-bit 2-2 MASH delta-sigma modulator (DSM) for the isolated amplifier. Combining the cascade of integrators with feedforward (CIFF) structure and the cascade of integrators with feedback (CIFB) structure, the DSM effectively results in reduced harmonic distortion. Gain boost and slew rate (SR) boost techniques are used to enhance the performance of the first stage integrator. To reduce low-frequency noise, the chopper technique is adopted as well. The DSM was fabricated in a 0.18 μm CMOS process with an active area of 0.90 mm2, dissipating 29.70 mW under a 3.3 V supply with the Schreier figure-of-merit (FoMs) 170.00 dB. The 108.71 dB signal-to-noise and distortion ratio (SNDR) and 17.77 bits the effective number of bits (ENOB) are achieved by simulation in a 20 kHz bandwidth.

Peripheral nerve stimulation informed design of a high-performance asymmetric head gradient coil.

Peripheral nerve stimulation (PNS) limits the image encoding performance of both body gradient coils and the latest generation of head gradients. We analyze a variety of head gradient design aspects using a detailed PNS model to guide the design process of a new high-performance asymmetric head gradient to raise PNS thresholds and maximize the usable image-encoding performance. A novel three-layer coil design underwent PNS optimization involving PNS predictions of a series of candidate designs. The PNS-informed design process sought to maximize the usable parameter space of a coil with <10% nonlinearity in a 22 cm region of linearity, a relatively large inner diameter (44 cm), maximum gradient amplitude of 200 mT/m, and a high slew rate of 900 T/m/s. PNS modeling allowed identification and iterative adjustment of coil features with beneficial impact on PNS such as the number of winding layers, shoulder accommodation strategy, and level of asymmetry. PNS predictions for the final design were compared to measured thresholds in a constructed prototype. The final head gradient achieved up to 2-fold higher PNS thresholds than the initial design without PNS optimization and compared to existing head gradients with similar design characteristics. The inclusion of a third intermediate winding layer provided the additional degrees of freedom necessary to improve PNS thresholds without significant sacrifices to the other design metrics. Augmenting the design phase of a new high-performance head gradient coil by PNS modeling dramatically improved the usable image-encoding performance by raising PNS thresholds.

A single-beat algorithm to discriminate farfield from nearfield bipolar voltage electrograms from the pulmonary veins

BackgroundSuperimposition of farfield (FF) and nearfield (NF) bipolar voltage electrograms (BVE) complicates the confirmation of pulmonary vein (PV) isolation after catheter ablation of atrial fibrillation. Our aim was to develop an automatic algorithm based on a single-beat analysis to discriminate PV NF from atrial FF BVE from a circular mapping catheter during the cryoballoon PV isolation.MethodsDuring freezing cycles in cryoablation PVI, local NF and distant FF signals were recorded, identified and labelled. BVEs were classified using four different machine learning algorithms based on four frequency domain (high-frequency power (PHF), low-frequency power (PLF), relative high power band, PHF ratio of neighbouring electrodes) and two time domain features (amplitude (Vmax), slew rate). The algorithm-based classification was compared to the true identification gained during the PVI and to a classification by cardiac electrophysiologists.ResultsWe included 335 BVEs from 57 consecutive patients. Using a single feature, PHF with a cut-off at 150 Hz showed the best overall accuracy for classification (79.4%). By combining PHF with Vmax, overall accuracy was improved to 82.7% with a specificity of 89% and a sensitivity of 77%. The overall accuracy was highest for the right inferior PV (96.6%) and lowest for the left superior PV (76.9%). The algorithm showed comparable accuracy to the classification by the EP specialists.ConclusionsAn automated farfield-nearfield discrimination based on two simple features from a single-beat BVE is feasible with a high specificity and comparable accuracy to the assessment by experienced cardiac electrophysiologists.Graphical

Power-Efficient Single-Stage Class-AB OTA Based on Non-Linear Nested Current Mirrors

A novel approach to design low-power area-efficient rail-to-rail output single-stage class-AB operational transconductance amplifiers (OTAs) with enhanced large- and small-signal performance to drive large capacitive loads is presented. It is based on a non-linear nested current mirror at the active load of a splitted differential input pair biased in weak inversion that boosts dynamic currents beyond their quiescent value directly at the output branch. As a result, slew rate, DC gain, gain-bandwidth product, settling time and noise performance are improved without additional circuit elements or power consumption. An OTA prototype has been fabricated in a 180-nm CMOS process, consuming a quiescent power of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2.9~\mu \text{W}$ </tex-math></inline-formula> from a supply voltage of ±0.5 V and a silicon area of 0.001 mm2. Measurement results validate the advantages of the proposal, exhibiting positive and negative slew rates of 110 V/ms and −58 V/ms, respectively, and a gain-bandwidth product of 136 kHz with a phase margin of 90° for a capacitive load of 160 pF.

PESNet 3.0: A WRN-Based Communication Network With ±0.5 ns Synchronization Error for Large-Scale Modular Power Converters

Emerging large-scale silicon-carbide (SiC)-based modular power converters are pursuing high-performance distributed control systems (DCSs). In particular, fast-switching-enabled novel control schemes raise the need for minimal synchronization error (SE) of communication networks. This article presents the development of a proposed power electronics system network (PESNet) 3.0 that features a sub-nanosecond (ns) SE and gigabits-per-second data rate. The White Rabbit Network (WRN) technology, originally developed for particle accelerators, has been embedded in PESNet 3.0 and tailored to be suited for large-scale high-frequency modular power converters. A simplified node-to-node phase-locked loop (N2N-PLL) and an improved precision time protocol (PTP) model has been proposed to lock both the frequency and phase of two independent clocks on two adjacent nodes. Subsequently, the stability analysis of the N2N-PLL is carried out with its closed-loop transfer function verified by digital perturbation injection (DPI). Finally, the experimental validation of PESNet 3.0 is demonstrated at both controller and converter levels. The latter is on a first-of-it-kind 10-kV SiC-MOSFET-based modular converter prototype operating at 12-kV dc-link voltage, 10-kHz switching frequency, and above 100-V/ns slew rate, verifying ±0.5 ns SE at 5 Gb/s data rate.

Behavioral Modeling and Circuit Design of High Precision Low Power Dynamic Zoom ADC

In this paper, a high-precision, energy-saving dynamic zoom ADC consisting of a 6-bit SAR ADC and a second-level Σ − ∆ modulator (SDM) is proposed. Non-ideal factors, including slew rate (SR), limited bandwidth and DC gain of the op-amp, and kT/C noise, mismatch of DAC capacitors, are analyzed with a behavioral model in Simulink to guide actual circuit design more accurately. The ADC parameters are adjusted and optimized by model simulation. Because the DAC capacitors mismatch produces harmonic distortion, the DWA technique is used. A new digital combined circuit is proposed to minimize power consumption. To further improve its energy efficiency, a gain enhancement current mirror OTA is designed and the SAR ADC adopts upper plate sampling technique. The layout of zoom ADC occupies 0.856 mm2 in 65 nm techniques. It achieves 109.2 dB SNDR, 17.84 bits ENOB at 1 kHz signal bandwidth and consumes only 0.233 mW.

An active swing suppression control scheme of overhead cranes based on input shaping model predictive control

An input shaper-based model predictive control scheme is proposed for an overhead crane to suppress the swing of the payload. A control-oriented mathematical model of the crane is firstly derived based on the small angle hypothesis. Furthermore, three kinds of commonly used shapers are discussed and a zero vibration derivative shaper is selected for the crane. Then, a model predictive swing suppression controller is designed for the crane based on the selected shaper. Constraints on the control input and its slew rate are respected. Besides, the constraint on the swing angle of the payload is also respected as an output constraint. The constrained solution is given in the form of standard quadratic programming. The designed control scheme combines open-loop and closed-loop control techniques, achieving accurate positioning of the trolley and good swing suppression of the payload. A series of simulation demonstrates the effectiveness and advantages of the proposed scheme.

Discrete event simulation of vessel stationkeeping operations in ice-rich waters

This paper describes a high-fidelity numerical model that simulates vessel stationkeeping operations in ice-rich waters. The discrete event simulation engine incorporates several novel features, including new ice floe failure models for bow and midships locations; an ice floe creation strategy that facilitates rafting of ice floes; and a vessel thruster model that takes into account physical limitations such as thruster angle slew rates and propeller ramp rates. It accommodates a wide range of ice field specifications and runs in real-time on a standard desktop personal computer (Intel® Core™ i7 Processor or equivalent). The model has been validated using physical measurements of a generic drillship model in several broken ice conditions; it predicted thruster forces and motions that were comparable to those observed during dynamic positioning operations.

A Low-Power, Fast-Transient FVF-Based Output-Capacitorless LDO with Push–Pull Buffer and Adaptive Resistance Unit

An output-capacitorless low-dropout regulator (LDO) with a push–pull buffer was presented in this paper. The proposed push–pull buffer was able to provide a large charge and discharge current to increase the slew rate at the gate of the power transistor effectively, thereby improving the transient response of this LDO. In addition, an adaptive resistance unit (ARU) was proposed to solve the right half-plane zero problem caused by Miller compensation to optimize the loop stability of the LDO. The proposed LDO was implemented in a 0.18-µm CMOS technology. Simulation results showed that the quiescent current of this LDO was only 16.1 µA. It regulated the output at 1.5 V from a 1.8 V supply, with a dropout voltage of 300 mV at the maximum output current of 50 mA. The maximum value of the voltage spike was 129 mV. Additionally, the recovery time of the LDO was 0.2 µs.

Streamwise Extent and Ramp Rate Effects on Laminar Boundary Layer Response to Plasma Actuator Vortex Generators

AbstractThe unsteady output of a spanwise array of plasma actuators, arranged to generate streaks of high and low streamwise velocity in a Blasius boundary layer, is modeled numerically. When the forcing by the actuators undergoes a step change from off to on, the flow response downstream of the actuators is initially inverted in terms of the streamwise vorticity, disturbance velocity, and wall shear stress before approaching the steady-state behavior. The present study considers the effect of the length of the actuator in the streamwise direction and the effect of the rate change of the output of the actuator with respect to the nonminimum phase behavior. For the different rates of a gradually applied force, the body force increases linearly from zero to the same maximum value of the step, which simulates a reduced slew rate or ramped output. It is shown that the inverse flow response remains for the gradually applied input; however, the peak magnitude is less, and the overall response appears more damped. As the actuator length is reduced, while forcing was compensated for the shorter convective time over the actuator, the peak inverse response was enhanced.

A Review of Techniques to Enhance an Amplifier’s Performance Using Resistive Local Common Mode Feedback

A review of some of the most common applications of the resistive local common mode feedback technique to enhance amplifier’s performance is presented. It is shown that this simple technique offers essential improvement in open loop gain, gain-bandwidth product, slew rate, common mode rejection ratio, power supply rejection ratio, etc. This is achieved without increasing power dissipation or supply voltage requirements and with small additional silicon area and circuit complexity. It is also shown that it is especially appropriate to improve amplifiers’ performance in current fine-line submicrometer CMOS technology. Some of the applications discussed are GB enhanced, class AB and super class AB operational amplifiers, gain boosted op-amps, bulk-driven circuits, sample and hold circuits and power management circuits, among others.

Determining the Zero-Temperature-Coefficient Point From Device Simulation to Circuit for Improving Temperature Variation Immunity

Thermal issue emerges as one of the critical reliability concerns in integrated circuit design, especially for advanced technology. To improve the temperature immunity and reduce the thermal-related timing guard bands in digital circuits, in this work, we offer a new insight into the zero-temperature-coefficient (ZTC) based design strategy featuring minimizing the temperature-induced delay variation. An effective current-based method to facilitate the ZTC point ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {ZTC}}$ </tex-math></inline-formula> ) determination for standard cells is developed, which is demonstrated on advanced gate-all-around (GAA) nanosheet (NS) FETs from 300 to 425 K using the calibrated TCAD simulation. The <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {ZTC}}$ </tex-math></inline-formula> dependencies on the signal input slew rate, output capacitance, and self-heating effects (SHEs) are further investigated from the perspective of the effective current by tracing the voltage trajectory. The mixed-mode TCAD simulation results show that the frequency variation of ring oscillator (RO) reduces nearly ten times when operating near <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {ZTC}}$ </tex-math></inline-formula> and great power-performance trade-offs can also be achieved. The <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {ZTC}}$ </tex-math></inline-formula> determination for standard cells combined with the compensation effect among different standard cells benefits selecting the optimal zero-temperature-delay (ZTD) point in the target path, thereby helping to implement a robust digital design against temperature variation.

A 2xVDD digital output buffer with gate driving stability and non-overlapping signaling control for slew-rate auto-adjustment using 16-nm FinFET CMOS process

This paper presents a 2 × VDD mixed-voltage digital output buffer where its slew rate (SR) is automatically adjusted based on PVT (process, voltage, and temperature) detection. The developed buffer is the first to be fabricated using TSMC 16-nm CMOS Logic FinFET Compact (Shrink) LL ELK Cu 1P13 M process. Since slew rate is one of the major required parameters in many interfacing protocols, it is really hard to meet if the mixed-voltage output buffer is needed in FinFET processes. The major reason is the low VDD in these advanced processes. However, our buffer's SR is improved by implementing low threshold voltage (Vth) type of device for always-on driving transistors in the Output Stage, thereby increasing the output current. Moreover, since FinFET devices were used in the buffer, the stability of the gate drives of the said driving transistors must be ensured so that noise interference will be avoided. Lastly, the buffer's Timing Shifters used non-overlapping signaling control directly implemented at the transistor level to eliminate the errors caused by delay variations. Based on silicon measurement results, at a load capacitance of 20 pF, the said circuit can be operated at a maximum data rate of 250 MHz for both supply voltages of 0.8 and 1.6 V (namely external VDD or VDDIO), respectively. When the SR auto-adjustment is activated, the SR improvement is at least 49.2% and 37.5% for 0.8 and 1.6 V, respectively.

Exploring Topological Semi-Metals for Interconnects

The size of transistors has drastically reduced over the years. Interconnects have likewise also been scaled down. Today, conventional copper (Cu)-based interconnects face a significant impediment to further scaling since their electrical conductivity decreases at smaller dimensions, which also worsens the signal delay and energy consumption. As a result, alternative scalable materials such as semi-metals and 2D materials were being investigated as potential Cu replacements. In this paper, we experimentally showed that CoPt can provide better resistivity than Cu at thin dimensions and proposed hybrid poly-Si with a CoPt coating for local routing in standard cells for compactness. We evaluated the performance gain for DRAM/eDRAM, and area vs. performance trade-off for D-Flip-Flop (DFF) using hybrid poly-Si with a thin film of CoPt. We gained up to a 3-fold reduction in delay and a 15.6% reduction in cell area with the proposed hybrid interconnect. We also studied the system-level interconnect design using NbAs, a topological semi-metal with high electron mobility at the nanoscale, and demonstrated its advantages over Cu in terms of resistivity, propagation delay, and slew rate. Our simulations revealed that NbAs could reduce the propagation delay by up to 35.88%. We further evaluated the potential system-level performance gain for NbAs-based interconnects in cache memories and observed an instructions per cycle (IPC) improvement of up to 23.8%.

Performance parameters optimization of CMOS analog signal processing circuits based on smart algorithms

Designing ideal analogue circuits has become difficult due to extremely large-scale integration. The complementary metal oxide semiconductor (CMOS) analog integrated circuits (IC) could use an evolutionary method to figure out the size of each device. The CMOS operational transconductance amplifier (CMOS OTA) and the CMOS current conveyor second generation (CMOS CCII) are designed using advanced nanometer transistor technology (180 nm). Both CMOS OTA and CMOS CCII have high performance, such as a wide frequency, voltage gain, slew rate, and phase margin, to include very wide applications in signal processing, such as active filters and oscillators. The optimization approach is an iterative procedure that uses an optimization algorithm to change design variables until the optimal solution is identified. In this study, different sorts of algorithms the genetic algorithm (GA), particle swarm optimization (PSO), and cuckoo search (CS) are employed to boost and enhance the performance parameters. While decreasing the time required to develop a conventional operation amplifier's settling time. Some studies decrease the value of the power utilized at various frequencies. Others operate at extremely high frequencies, but their power consumption is greater than that of those operating at lower frequencies.

Efficiency Analysis and Design Considerations of a Hysteretic Current Controlled Parallel Hybrid Envelope Tracking Power Supply

This paper presents the realization of an Envelope Tracking Power Supply (ETPS), for a sinusoidal envelope input signal. A parallel hybrid topology is chosen for the implementation. In this topology, a voltage-controlled Class-AB linear amplifier stage and a current-controlled switching converter stage operate in parallel. A hysteretic current control scheme is employed to control the operation of the switching converter. Block-level implementation of the ETPS is done using Simulink 2017b, continuous mode simulation. Simulations are performed using a sinewave input envelope signal = 1.94+ 1.2 sin(ω∙t). The input frequency varied from 1MHz to 60MHz. As the input frequency is increased, the ETPS moves from the linear to the non-linear region of operation. During the transition, the slew rates of the load current and the switching current match at a particular input frequency of 2MHz while the efficiency peaks. The maximum obtained efficiency while tracking the sinewave input signal is 82.3%. The way the efficiency can be optimized by focusing on the matching of the slew rates of load and switching currents is explained. Also, an insight into the study of various circuit parameters and the trade-offs that the designer needs to consider while designing an ETPS, is provided.

Analysis and Comparison of Two Stage and Single Stage Operational Amplifiers Using 0.18µm Technology

Operational amplifier exists in many numbers of configurations. The there are many types of the Operational amplifiers. These are: two stage, single stage, three stage and multistage amplifiers. Identifying the better op amp is important to get better application. The better op amp will be selected by considering the performance parameters (DC Gain, Slew Rate, Power Dissipation, etc.) of op amp. In project work a two stage cmos and single stage CMOS operational has been compared and contrasted based on values of their performance parameters by using 0.18µm CMOS technology and the same power supply (5V). Based on these values, By comparing the performance parameters single stage CMOS op amp is more stable and operate longer duration of time than two stage cmos op amp with small energy loss; while two stage op amp produces the output which is twice larger than single stage op amp, and also the noise in the output of two stage op amp is less than single stage op amp. So to get more output it is better to use two stage op amps. By results and reasons suitable choices for high gain and high performance applications are two stage topologies.

Design and analysis of DTMOS based RFC with controlled positive feedback OTA using HSCCM and adaptive biasing technique

In this paper, DTMOS based recycling folded cascode with controlled positive feedback operational transconductance amplifier is introduced. The proposed Positive Feedback Recycling Folded Cascode Operational Transconductance Amplifier (PFRFC OTA) employs positive feedback which enhances and controls the dc gain of PFRFC OTA by adjusting current in feedback. The proposed PFRFC OTA also utilizes the high swing cascode current mirror (HSCCM) as active load which provides high output impedance at low power supply requirements. Moreover, the adaptive biasing is provided by using cross-coupled flipped voltage followers to the differential pair which results in remarkable improvement in gain, unity gain bandwidth and slew rate. The flipped voltage followers are also utilized to reuse the input current to drive the transistors which are connected in feedback with HSCCM. The proposed PFRFC OTA employs PMOS DTMOS transistors at the input stage which utilizes the body effect to enhance the performance of the proposed amplifier. The proposed PFRFC OTA with the second stage is also implemented to further improve the frequency response of the proposed circuit. Mentor Graphics Eldo tool with CMOS technology of 0.18 μm is used for the simulation of the proposed circuits at supply voltage of ±0.5 V. The simulation result of the proposed PFRFC OTA provides gain of 90 dB and a power consumption of 42 μW. The proposed two stage PFRFC OTA provides gain of 114.56 dB. To validate the efficiency of the proposed two stage PFRFC OTA, a tunable biquad filter is also implemented.

Correction method for walk error based on the shape of reflective surface in LiDAR

Walk error produced in light detection and ranging (LiDAR) based on the time-of-flight (TOF) leads to loss of ranging accuracy. Walk error, which is systematic and correctable, is mainly attributed to the distance to the target, reflectance, the shape of reflective surface, and so on. In particular, various shapes of received pulse based on the shape of reflective surface have a considerable effect on the ranging accuracy. In this paper an incoherent pulsed laser echo equation for different shapes of reflective surface is established and it is found that parameters that can represent various shapes of received pulse involve received pulse width and slew rate. A measurement method of pulse width and slew rate combining a constant fraction discriminator (CFD) principle with a time over threshold (TOT) is proposed. It is also found that the proposed method is more efficient in walk error correction than the TOT by obtaining walk error corrections corresponding to pulse width and slew rate and determining the corresponding 2D surface polynomial coefficients. The obtained polynomial coefficients are used to ensure the ranging accuracy of the LiDAR within ± 3 cm.