Slave Module Research Articles

FASTBUS simulation tools

A generalized model of a FASTBUS master is presented. It is used with simulation tools to aid in the specification, design, and production of FASTBUS slave modules and provides a mechanism to interact with the electrical schematics and software models to predict performance. The model is written in the IEEE Std 1076-1987 hardware description language VHDL. A model of the ancillary timing controller (ATC) logic is also presented. VHDL was chosen to provide portability to various platforms and simulation tools. The models, in conjunction with most commercially available simulators, will perform all of the transactions specified in IEEE Std 960-1989. The models may be used to study the behavior of electrical schematics and other software models and detect violations of the FASTBUS protocol. The master model accepts a stream of high-level commands from an ASCII file to initiate FASTBUS transactions. Using this standard-base command language to direct the model of the master, hardware engineers can simulate FASTBUS transactions in the language used by physicists and programmers to operate FASTBUS systems. >

A Distributed Architecture for Telecontrolled Underwater Operation

This paper presents some Underwater Robotics activities carried on at the Naval Automation Institute (IAN) of the Italian National Research Council. In particular it discusses the set-up of a testbed underwater vehicle (ROBY) devoted to experimental activity in the field of oceanology. ROBY is designed to develop autonomous or semi-autonomous functions although a physical link exists between the control station (MASTER) and the actual widerwater module (SLAVE). The SLAVE module has to accomplish three main tasks: communications handling, data logging and tight loop control. The MASTER module performs high level operations like navigation planning and control. The implementation of such a distributed architecture has also required the development of high speed reliable communication channels.

The TSU: a FASTBUS module for the TOF detector of DELPHI

In this paper we describe a FASTBUS slave module for application with the time of flight detector of DELPHI. The module deals with the information obtained in photomultipliers and performs discrimination, mean timing for trigger tasks as well as time digitization with readout features.

Fast data acquisition with the CDF event builder

The CDF (Collider Detector at Fermilab) event builder is an intelligent FASTBUS device that performs parallel readout of a set of FASTBUS slaves on multiple-cable segments, formats the data, and writes the reformatted data to a FASTBUS slave module. The authors review the properties of this device and summarize its performance in the CDF data acquisition system. Preliminary performance of the prototype is being evaluated, and an event rate of approximately 30 Hz appears possible in the near future.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Interfacing slave designs to FASTBUS: practical experience

The authors have designed a number of FASTBUS slave modules, using a standard interface circuit and standard design-verification tools based on computer-aided-engineering (CAE) techniques. They describe the standard interface and the design and verification methodology. The interface logic for FASTBUS slaves is divided into three blocks: the slave control logic, slave address/data logic, and slave support logic. The control logic is a hybrid chip that handles the protocol portion of the interface. The slave address/data logic includes the functions performed by the address/data interface chip and additional data-path related components, i.e. registers, buffers, and level shifters. The support logic is additional logic necessary to glue the other blocks and application logic together. >

Computer architecture for intelligent robots

AbstractThis article proposes a computer architecture suitable for intelligent robots, especially for self‐contained intelligent mobile robots. The main principles proposed by the authors are: (1) The robot should be a multiprocessor system with a master, several slave modules and a console. A simple star connection is employed. (2) The master carries user's programs written in a high level language with which a programmer is able to use all basic functions in the robots. It should have a special purpose operating system. (3) Each module is an independent microcomputer system loosely coupled to the master and dedicated to an elementary function such as manipulation, locomotion, sensing, or planning. (4) A serial TTL level or RS232C interface is employed between the master and each module. Two self‐contained robots, Yamabico 9 and 10, constructed under these design principles have demonstrated the effectiveness of this proposed architecture.

A Simple FASTBUS Slave Interface Using PALs

In any bus system, it is desirable to implement the basic bus protocol with a standard interface. The paper describes such an interface which has been developed for FASTBUS Slave modules. The interface supports all FASTBUS Address and Data Cycles. Major parts of the interface have been implemented in programmable array logic (PALs*) which reduces the space occupied by the interface to less than 10% of the board area.

A General Purpose FASTBUS Interface Chipset

A design concept is presented for a set of semicustom integrated circuits which will interface a master or slave module to a FASTBUS segment. These devices will perform master arbitration, address recognition, handshaking, data pipe-lining and many other standard FASTBUS protocol tasks. Gate arrays are used to implement designs which would require one hundred or more normal integrated circuits, thus greatly reducing the area of a FASTBUS printed circuit board needed for the interface.

FASTBUS Slaves -- A Designers View

Although FASTBUS has features built into it which allow complex interconnections and multiple Masters, the rules for implementing Slaves are very simple. The first time designer of Slave Modules should not be intimidated by the 200 pages of the FASTBUS document. About 90% of the specification is associated with system implications that do not impact Slave design. This paper will review the basic logic and timing requirements for FASTBUS Slave design. Also, some examples of implementation will be shown. The discussion which follows assumes that mastership of the bus has been gained. Bus arbitration, system interconnection, message routing, etc. are separate topics and will not be discussed here. These topics affect only the design of devices which operate at the system level since FASTBUS Slave modules have been specified to be completely transparent to these system considerations.