Capacitor Size Research Articles

A probabilistic multi-objective approach for FACTS devices allocation with different levels of wind penetration under uncertainties and load correlation

This study presents a probabilistic multi-objective optimization approach to obtain the optimal locations and sizes of static var compensator (SVC) and thyristor-controlled series capacitor (TCSC) in a power transmission network with large level of wind generation. In this study, the uncertainties of the wind power generation and correlated load demand are considered. The uncertainties are modeled in this work using the points estimation method (PEM). The optimization problem is solved using the Multi-objective particle swarm optimization (MOPSO) algorithm to find the best position and rating of the flexible AC transmission system (FACTS) devices. The objective of the problem is to maximize the system loadability while minimizing the power losses and FACTS devices installation cost. Additionally, a technique based on fuzzy decision-making approach is employed to extract one of the Pareto optimal solutions as the best compromise one. The proposed approach is applied on the modified IEEE 30-bus system. The numerical results evince the effectiveness of the proposed approach and shows the economic benefits that can be achieved when considering the FACTS controller.

Placement of Distributed Generation and Shunt Capacitor in Distribution Network using Cuckoo Search Algorithm

This work aims at reduction in active and reactive power loss reduction in distribution networks as well as to improve the voltage stability of the networks. Optimum Distributed Generation (DG) placement and sizing is carried out in conjunction with shunt capacitor placement and sizing to determine the appropriate sizes of DG units and Capacitor banks to be placed in the networks so as not to violate certain constraints. The optimal sizes of the DG units and capacitor banks were obtained on application of a Cuckoo Search Optimization Algorithm while computations for Voltage stability was performed using the Voltage Stability Index (VSI). The obtained optimal sizes of DG units and Capacitors were individually and simultaneously placed on the distribution networks to ascertain the behaviour of the networks prior to and after their placements. The performance factors considered are power loss and voltage stability. A comparison of these performance factors under separate and simultaneous placement method was demonstrated using IEEE 33 and 69 test buses. Result show that power loss (active and reactive) reduced by 63.29% and 59.38% respectively for 33 bus system, with a 74.29% and 79.19% reduction on 69 bus system. Voltage stability also increased by 7.89% and 3.79% respectively for 33 and 69 bus system relative to values obtained for base case and separate DG and shunt capacitor placement.
 Keywords: Distributed generation, shunt capacitor, Cuckoo Search Algorithm (CSA), power loss and voltage stability.

The Thyristor-Augmented Modular Bridge Converter: A Highly Efficient VSC-HVDC Converter With Reduced Energy Storage Requirement

Recently, the idea of combining both thyristors and IGBTs in a voltage-source converter (VSC) structure has gained significant research interests for HVDC applications. The main objectives of deriving these topologies are to achieve forced-commutation of thyristors, increased efficiency, reduced energy-storage requirement and dc-fault tolerance besides retaining the VSC control flexibility. A novel topology named `thyristor-augmented modular bridge converter' (TAMBC) is proposed in this paper. Each TAMBC phase contains four chain-links comprising of series-connected stacks. Each stack contains a parallel connection of an IGBT-based submodule-branch and a thyrsitor-branch. A control technique is developed that allows the main current to flow primarily through the thyrsitor-branch to achieve higher efficiency. In each phase of TAMBC, two chain-links generate the required ac voltage in the first half-cycle and are bypassed through thyrsitor-branch during the next half-cycle. Consequently, it enables current distribution among the chain-links resulting in reduced capacitors size and enhanced efficiency. The ability of TAMBC-HVDC systems to function over a wide operating range, to ride-through ac faults and to provide independent active and reactive power control are verified using PSCAD. Capacitors design, loss analysis and comparative evaluations are carried out to highlight the key features of the TAMBC over the existing ones.

Comparison Study of DAC Realizations in Current Input CTΣΔ Modulators

In this brief, a comparison between five different DAC realizations is presented for an equivalent multi-MΩ range resistance in a digitizing current sensor, namely resistor, current source, pseudo-resistor, T-network resistor, and switched-capacitor-resistor (SCR). These DACs are needed to realize current input continuous-time sigma-delta modulator (C-CTΣΔM) readouts to sense currents in the pA range. All DAC realizations are discussed concerning disadvantages and advantages and are implemented, laid out, and simulated on transistor level in a 180nm CMOS technology. The comparison is carried out on the area consumption, required circuit overhead, noise performance, inherent anti-aliasing filter (AAF) quality, and two sources of non-idealities (clock jitter and ISI). It is shown that the SCR-DAC - due to its decaying waveform and its inverse proportionality of the equivalent resistance to its capacitor size - shows the best compromise over the other methods and achieves the best performance in the smallest area.

Multi-objective optimization of optimal capacitor allocation in radial distribution systems

Abstract The optimal size and location of the compensator in the distribution system play a significant role in minimizing the energy loss and the cost of reactive power compensation. This article introduces an efficient heuristic-based approach to assign static shunt capacitors along radial distribution networks using multi-objective optimization method. A new objective function different from literature is adapted to enhance the overall system voltage stability index, minimize power loss, and to achieve maximum net yearly savings. However, the capacitor sizes are assumed as discrete known variables, which are to be placed on the buses such that it reduces the losses of the distribution system to a minimum. Load sensitive factor (LSF) has been used to predict the most effective buses as the best place for installing compensator devices. IEEE 34-bus and 118-bus test distribution systems are utilized to validate and demonstrate the applicability of the proposed method. The simulation results obtained are compared with previous methods reported in the literature and found to be encouraging.

Significant Implication of Optimal Capacitor Placement and Sizing for a Sustainable Electrical Operation in a Building

The improvement of energy efficiency plays an important role to ensure sustainable electrical operation in large-scale buildings. In relation to the low-cost electrical components, a capacitor is an electrical component that can be used to sustain or improve the operating performance of an unbalanced electrical system in large-scale buildings so that energy efficiency improvement can be obtained. This is important to overcome the ineffective utilization of energy caused by the occurrence of power losses in an unbalanced electrical system of large-scale buildings. Further improvement of energy efficiency can be obtained by reducing an excessive amount of incoming power through the determination of tap setting for incoming transformer, and this is classified under the concept of conservative voltage regulation (CVR) approach. In order to solve the problem, the optimal capacitor placement and sizing (OCPS) with CVR is introduced as a new approach for energy efficiency improvement while ensuring a sustainable operation in an unbalanced electrical system of large-scale buildings. The proposed technique utilizes the artificial intelligence (AI) based differential evolution particle swarm optimization (DEPSO) technique with the objective function of total cost minimization for the real power losses, real power consumption, and capacitors installation. The effectiveness of the proposed technique to achieve energy efficiency improvement is investigated through a case study of an unbalanced electrical system in a large-scale office building. The significance of the research output is related to its low-cost technology that has the potential for a comprehensive, pragmatic implementation in large-scale buildings, and subsequently, it will significantly accelerate the increase of national agenda in energy efficiency.

Integration of DG and Capacitor in Radial Distribution Networks Using an Efficient Hybrid Optimization Method

Recently, integration of distributed generations (DGs) and shunt capacitors in radial distribution network are becoming popular to withstand the rapidly increasing in electricity demands. In this article, a hybrid method is proposed to obtain the best locations and sizes of capacitors and DGs in radial distribution network. This hybrid method is based on chaotic whale optimization algorithm (CWOA) and loss sensitivity factor (LSF). The proposed method is tested on IEEE 69-bus system to enhance the buses voltages, increase the distribution system capacity, and decrease the total power loss. The obtained results prove that the proposed method based on CWOA and LSF can be highly effective in determining the locations and sizes of capacitors and DGs in RDS compared with other optimization techniques.

Energy Savvy Network Joining Strategies for Energy Harvesting Powered TSCH Nodes

This article presents methods that enable batteryless energy harvesting powered time-synchronized channel hopping (TSCH) wireless sensor nodes to join a network with less energy wastage. Network joining of TSCH nodes is very power hungry yet inevitable process to form a working wireless sensor network (WSN). Since the energy level from energy harvesting is scarce, energy passive methods are essential. A duty-cycled network joining process in combination with an appropriate capacitor size is proposed here as they are among the factors that can be easily controlled without extra energy. When a node joins the network in a duty-cycled manner, other nodes may join the network during the gap time, which reduces energy wastage of the nodes in waiting. With an appropriate capacitor size, the capacitor can be charged up within a reasonable time and power up the node for a sufficiently long time, which increases the probability to complete the network joining process of the node. With the combination of a join duty cycle of 50% with a 100-mF capacitor, a WSN was successfully formed by two energy harvesting powered wireless sensor nodes in one network joining attempt.

CHANCE: Capacitor Charging Management Scheme in Energy Harvesting Systems

The energy efficiency of emerging nonvolatile processors equipped with FRAM-SRAM memory makes them a promising solution for energy harvesting systems. To enable correct functionality and forward progress with an unreliable power supply, the system must accumulate sufficient energy in the capacitor to execute tasks atomically, even in the worst case scenario. Due to the large gap between the average and worst case energy consumption of tasks, state-of-the-art approaches like eM-map require a large capacitor to execute tasks on the SRAM. However, the size, cost, and charging time of the capacitor are major concerns in the energy harvesting systems. In this article, we proposed CHANCE, a capacitor charging management scheme that improves the capacitor size and average response time of an energy harvesting system. CHANCE analyses the energy consumption of tasks to set an appropriate capacitor size to make a balance between capacitor charging time and failure rate for each task. The results show that CHANCE improves the response time of state-of-the-art approaches up to 68% with a five times smaller capacitor.

Sizing of dc-link capacitor for a grid connected solar photovoltaic inverter

Objective: To determine the optimum size of a dc-link capacitor for a grid connected photovoltaic inverter. Methods: Dc-link capacitors are considered as one of the sensitive parts of the grid connected photovoltaic systems and needs effort to design a reliable and optimal size capacitor as its reliability is concerned with the overall system reliability. The double line frequency power flows between the input and outside of a Φ grid connected PV system which produces voltage ripples at the capacitor and dc link. This voltage ripple increases temperature of passive components and dc source which affects the MPP operation of the photovoltaic modules and the system life. Therefore, it is essential to limit the voltage ripples at the input side of the system. The easiest way to limit the double frequency ripple voltage is to connect a capacitor in parallel to the PV module and the inverter which buffers the double line frequency power and supply a constant power to the inverter. This study proposed a general method for sizing a dc-link capacitor for a Φ grid connected voltage source inverter. It is seen that the capacitance is inversely proportional to the nominal dc and ripple voltage. Thus an increase in the nominal system voltage decreases the size of the capacitor and at the same time increases the voltage ripple. Therefore to limit voltage ripple within permissible limits and to ensure better system performance the dc-link capacitor must be appropriately sized. The simulations based on 3kW grid connected PV system are carried out in DIgSILENT Power Factory software. Findings: A capacitor of 410µF is needed to be connected in parallel with a 3kVA inverter having an nominal input voltage of 370V and maintaining a voltage ripple under 8.5%. Novelty: After determining optimized dc-link capacitor size we will limit the voltage ripple under permissible limits and hence improves the system efficiency and life of the grid connected PV system. Keywords: Voltage source inverter; voltage ripple; Dc-link capacitor sizing; distributed generation; grid connected PV system

Capacitors Allocation in Distribution Systems Using a Hybrid Formulation Based on Analytical and Two Metaheuristic Optimization Techniques

In this paper, a hybrid optimization technique based on analytical and two heuristic methods is developed and applied to determine the optimal allocation of shunt capacitors into distribution systems, aiming to minimize the total power loss and energy cost. The developed technique is a combination of analytical technique based on Loss Sensitivity Factor (LSF) and two recent metaheuristic optimization techniques called Salp Swarm Algorithm (SSA) and Sine Cosine Algorithm (SCA). LSF with a fuzzy logic controller is utilized to determine the candidate buses while the hybrid approach based on SSA and SCA (SSA_SCA) is used to find the optimal capacitor size. The performance of developed technique is investigated using 15-bus, 69-bus, 85-bus, and East Delta Network EDN 30-bus distribution systems. The results of developed technique are compared with those obtained by other comparative optimization methods. The results show the superior of developed technique in determining the optimal allocation of capacitor.

Quadratic boost converter with low‐output‐voltage ripple

This study proposes a non-isolated quadratic boost converter (QBC) that features a low-output-voltage ripple with respect to traditional QBCs. This advantage is in contrast with other topologies that require a higher amount of stored energy by capacitors to achieve the same output-voltage ripple specification. This benefit permits to design a compact converter, since the size of capacitors is proportional to their energy storage rating. Moreover, the proposed transformerless topology is suitable for applications that require high-voltage gains as in the case of renewable energy applications. The main properties of the converter are corroborated as well as its advantages by providing mathematical models, analytical waveforms and experiments.

The Essence of the Little Box Challenge-Part A: Key Design Challenges & Solutions

In order to expedite the development of power electronic systems towards higher power density and efficiency at a lower cost of implementation, Google and IEEE initiated the Google Little Box Challenge (GLBC) aiming for the worldwide smallest 2 kVA / 450 V DC / 230 V AC single-phase PV inverter with η > 95 % CEC weighted efficiency and an air-cooled case temperature of less than 60 °C by using latest power semiconductor technology and innovative topological concepts. This paper, i.e., Part A of a discussion of The Essence of the Little Box Challenge, documents all important RD Part B is intended to convey the main findings and lessons learned from the participation in the GLBC. First, the key technical challenges of the GLBC are discussed and the technologies and concepts selected by the authors among different options are described in detail. Relevant design considerations, such as constant frequency pulse width modulation (PWM) or triangular current mode (TCM) operation of the bridge-legs, selection of power semiconductor technology, interleaving of bridge-legs, sizing of the power buffer capacitor, limitation of ground/leakage currents, etc., to achieve an ultra-compact implementation are discussed. Based on this overview, two promising inverter concepts to tackle the GLBC, (i) an H-bridge based inverter with DC-link referenced output filter and (ii) a DC/|AC| buck-stage with series-connected low-frequency (LF) |AC|/AC unfolder inverter, are then analyzed in detail. Based on the results of a multi-objective ηρ-Pareto optimization, a comparative evaluation of the performance in terms of efficiency (η) and power density (ρ) of the two considered inverter concepts is provided. It is shown that with the DC/|AC| buck-stage and |AC|/AC H-bridge unfolder inverter operated with 140 kHz PWM a power density of 14.7 kW/dm 3 (240 W/in 3 ) with a maximum efficiency of 98.1% at 2 kW output power can be achieved. These claims are then verified in Part B by means of experimental results obtained from prototype realizations and compared to the achievements of other GLBC finalists. The conclusions are of general importance and are providing key guidelines for the future development of ultra-compact power electronic converters.

Energy-Aware Sensing on Battery-Less LoRaWAN Devices with Energy Harvesting

Billions of Internet of Things (IoT) devices rely on batteries as the main power source. These batteries are short-lived, bulky and harmful to the environment. Battery-less devices provide a promising alternative for a sustainable IoT, where energy harvested from the environment is stored in small capacitors. This constrained energy storage and the unpredictable energy harvested result in intermittent on–off behavior of the device. Measuring and understanding the current consumption and execution time of different tasks of IoT applications is crucial to properly operate these battery-less devices. In this paper, we study how to properly schedule sensing and transmission tasks on a battery-less LoRaWAN device. We analyze the trade-off between sleeping and allowing the device to turn off between the execution of application tasks. This study allows us to properly define the device configuration (i.e., capacitor size) based on the application tasks (i.e., sensing and sending) and environmental conditions (i.e., harvesting rate). We define an optimization problem that determines the optimal capacitor voltage at which the device should start performing its tasks. Our results show that a device using LoRaWAN Class A can measure the temperature and transmit its data at least once every 5 s if it can harvest at least 10 mA of current and uses a relatively small capacitor of 10 mF or less. At harvesting rates below 3 mA, it is necessary to turn off the device between application cycles and use a larger supercapacitor of at least 140 mF. In this case, the device can transmit a temperature measurement once every 60–100 s.

Effect of the DC-Link Capacitor Size on the Wireless Inductive-Coupled Opportunity-Charging of a Drone Battery

Wireless inductive-coupled power transfer and opportunity battery charging are very appealing techniques in drone applications. Weight and size are very critical constraints in drones, so the battery and the on-board electronics must be as light and small as possible. The on-board components involved in the resonant inductive-coupled wireless power transfer usually consist of the secondary coil, the compensation capacitor, the bridge rectifier, the LC-filter and the battery. This paper suggests a sizing of the LC-filter capacitor that improves the charging power of the battery. In addition, further on-board space and size is saved by using the stray inductance of the battery as filtering inductor. LTSpice simulations and experimental tests carried out on the prototype of a wireless power transfer circuit shows the dependency of the power delivered to the battery on the filter capacitor size. Finally, it is found that the power transfer to the battery is maximized by choosing the capacitor value that sets the LC-filter resonant frequency close to the double of the excitation frequency of the wireless charging. The drawback is a large current and voltage ripple in the battery.

Practical Submodule Capacitor Sizing for Modular Multilevel Converter Considering Grid Faults

Submodule (SM) capacitors are key elements in the modular multilevel converter (MMC), the design of which influences the entire system performance. In practical cases, SM capacitor sizing must consider the abnormal system operation (e.g., grid faults). In order to find a clear design boundary for SM capacitors, a practical capacitor sizing method is presented for the first time in this paper, considering the grid-fault-ride-through operation of the MMC, impact of MMC control system, and aging mechanism of capacitors. The SM capacitor rated voltage, capacitance, ESR, thermal resistance, and lifetime can be decided to ensure reliable operations of the MMC during grid faults. The effectiveness of the proposed method has been verified through experimental tests on a down-scale MMC system.

A substitution method for nanoscale capacitance calibration using scanning microwave microscopy

This paper presents a calibration method and an uncertainty budget for capacitance measurements performed on micrometric size capacitors at microwave frequencies and nanometric resolution using a scanning microwave microscopy (SMM). The method applies the classical one-port vector network analyzer calibration for SMM using three known capacitance standards. These standards are established from a commercial calibration kit placed close to the microcapacitors in order to be calibrated. The calibration kit is composed of a large number of Metal-Oxide-Semiconductor (MOS) microcapacitors with capacitance values C ranging from 0.1 fF to 8.6 fF. Diligent selection criteria were established for the choice of the three capacitors. Their capacitance values were calculated from the AFM measured values of the area of the top electrodes and the dielectric thickness and considering the contribution of fringing fields. The combined type uncertainty on these calculated values amounts between 5% and 14% in relative value (uncertainty given at one standard deviation). The comparison between the capacitance values measured on calibration kit capacitors using the calibrated SMM and the calculated values show a good agreement for capacitances higher than 0.8 fF within uncertainties varying between 6% and 9%. For smaller capacitances, most of the observed deviations are not significant at two standard deviations. The uncertainties are mostly dominated by dimensional measurements and less importantly by unwanted capacitance effects. Based on these results, capacitances of two sets of microcapacitors were calibrated. The combined uncertainties vary from 14% to 7% for capacitances ranging from 0.1 fF to 3.1 fF respectively. The permittivity values of the dielectric layer of the two samples have been determined. They are found equal to 4.0 and 4.1 with a standard uncertainty of 0.6 and correlate with the expected value of 3.9.

Electrical Properties of Horizontal Array Capacitor Using Composite Organic Dielectric Layer of Impregnated Glass-Fiber Epoxy

We introduce a horizontal array capacitor with nine capacitances in a single body using an organic dielectric layer impregnated with glass fiber as a prepreg sheet. An organic solid horizontal array capacitor with a dielectric of prepreg materials of the epoxy type can implement the nine capacitances in a single body via a unique simple lamination and cutting process. We then investigate the basic electrical properties of a horizontal array capacitor. The organic solid array capacitors with five electrodes and four dielectrics are Cu/PPG layer/Cu/PPG layer/Cu/PPG layer/Cu/PPG layer/Cu with a horizontal array structure. The size of a completed array capacitor is 2.85 × 2.85 mm. The height of the fabricated array capacitor in the vertical direction is 0.5 mm, with nine capacitances possessing a series-type structure. The average capacitance value of C1, C2, C3, and C4 is 1.98 nF, and each tolerance has a value within 1% based on the average value. The temperature change rate in the capacitance maintains a nearly linear characteristic, but the rate of change tends to increase finely from 120°C or more. The capacitance values of C5, C6, and C7 with the parallel circuit were measured according to the voltage. Impedance and ESR (equivalent series resistor) of C1 were measured according to frequency and temperature.

A Four-Level Switching Scheme for SAR ADCs with 87.5% Area Saving and 97.85% Energy-Reduction

In this paper, a new highly energy-efficient switching scheme is presented for successive approximation register analogue-to-digital converters. The proposed method applies a four-level switching strategy to reduce the switching energy to one of the lowest levels reported yet. Also, the controller of this method has low complexity compared to the other procedures. In contrast to the conventional scheme, the switching energy is reduced by 97.85% and the total capacitor size is decreased by 87.5%. Moreover, under the condition of the 50-times Monte-Carlo simulation for capacitor mismatch and reference voltages mismatch (Vref/2 and Vref/4), the mean value of the effective number of bit (ENOB) with standard deviation of 1% is 7.4 and 7.33 bits, respectively, while the ENOB value without any mismatches is 7.51 bits with sampling frequency of 1MS/s. It is noteworthy that the Monte-Carlo simulations are performed in Spectre simulator in Cadence with consideration all of non-idealities such as transistor charge injection, clock jitter and clock feedthrough. In other words, accurate and electrical simulation is performed instead of behavioral simulation. As a result, the bar graph of the ENOB values is plotted in MATLAB. In addition, the maximum and minimum of DNL/INL values are between − 0.3/0.3 LSB.

A 0.35V 90nA Quiescent Current Output-Capacitor-Less NMOS Low-Dropout Regulator Using a Coarse-Fine Charge-Pump Circuit

In this brief, a low quiescent output-capacitor-less NMOS low-dropout regulator using a coarse-fine charge-pump circuit is proposed. The proposed charge-pump low-dropout regulator (CP-LDO) achieves the output-capacitor-less LDO using a NMOS power transistor, a comparator, and a coarse-fine charge-pump circuit. It reduces both the quiescent current and the capacitor size of the charge-pump by directly adjusting the gate voltage of the NMOS power transistor. It improves both the transient response and the quiescent power efficiency by coarsely and finely adjusting the gate voltage, respectively. This also can remove the output glitch voltage. The proposed CP-LDO was fabricated using a 65nm CMOS process. Its area is 0.01 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The maximum undershoot voltage is 108 mV when the load current changes from 0.5 mA to 10.5mA within the edge time of 1ns. The total capacitor of the CP-LDO is 7.6 pF. The quiescent current is 162 nA at VIN = 0.5 V and f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CLK</sub> = 1 MHz. The figure of merit is 0.0013 ps.