SiP Design Research Articles

Reliability Evaluation of a Low Loss Photodielectric

While market forces are affecting innovative package designs, the fundamental objectives of addressing reliability has remained the same. Regardless of package formation, the development focus is on material types, adhesion, stress, and thermal management. As packages move towards adopting automotive standards, protective passivation and insulation materials must demonstrate the ability to withstand stringent reliability at an early stage. Low dielectric polymers are applied as passivation materials. Their applications range in isolating signal-carrying conductors from each other, fast signal propagation, interlayer dielectrics to minimize resistance-capacitance (RC) time delays, crosstalk and power dissipation in high density and high-speed integration. This can range from mmWave to SiP and WLP designs as well as in optoelectronic designs wherein coupling between very close metal lines need to be suppressed to prevent degradation in device performance. A series of stress testing was completed to evaluate the mechanical, electrical, and thermal performance of low loss dielectric, PRL-029. Highly accelerated stress testing (HAST) assesses the reliability of insulator materials to protect copper structures. Electromechanical migration is a failure mode due to poor moisture resistance during electrical biasing and forced moisture uptake. To address these potential failure modes, HAST (JESD22-A110) at 130°C, 85% relative humidity, for 96 hours, was conducted with and without biasing at 5V. Pressure cooker testing (PCT) is an extreme test to determine when a material will fail by assessing humidity resistance. PCT (JESD22-A102-C) was run at 121°C, 100% relative humidity, 2 atmospheric pressure, for 96 hours total with a mid-point inspection at 48 hours. PRL-029 was coated, photopatterned, and developed to test the adhesion on various substrates. Due to the material’s low moisture uptake, the adhesion of the material did not degrade after PCT. To observe the copper protection performance, copper structures were fully covered by PRL-029. The sample ran through PCT and no dendrites, oxidation, or degradation of the copper was observed confirming protection. Additionally, the bulk film mechanical and dielectric properties of the sample were evaluated to see any shift in values. Young’s modulus, elongation, and tensile strength were evaluated at -55°C, ambient, 125°C, and 200°C, after hard cure and after 48 hours of PCT. The dielectric constant and dissipation factor from 28 to 50GHz were measured after cure and after 48 hours of PCT. The dielectric constant stayed consistent at approximately 2.6 from 28 to 50GHz. The dissipation factor increased by a factor of 1.3 from 0.003 to 0.004 after 48 hours of PCT from 28 to 50GHz. Temperature cycle testing (TC) (JESD22-A104 Grade 2) was performed to understand the endurance of exposure to extreme temperatures at -55°C and 125°C. Thermal mismatch between the resist and substrate can lead to cracking, warpage, and delamination. PRL-029 passed 2000 cycles of TC and the integrity of the bulk film properties did not deteriorate. A low loss dielectric material has been developed, capable of enduring reliability test standards that are required for current and next generation polymeric dielectric packaging designs.

Three-Dimensional SIP Design of the Four-Channel RF Transceiver Based on Silicon and ALN for X-Band Radar Applications

Three-Dimensional SIP Design of the Four-Channel RF Transceiver Based on Silicon and ALN for <i>X</i>-Band Radar Applications

Gap analysis and methodological framework to assess and develop water centric sustainable agricultural intensification pathways in Sub-Saharan Africa

The sustainable agricultural intensification (SAI) debate, partly rooted in discussions over the Green Revolution, was developed in the 1990s in the context of smallholder agriculture in Africa. In many Sub-Saharan African (SSA) countries, production is still largely rainfed, with the prevalence of significant yield gaps and rapid environmental degradation. Projections indicate that climate and demographic changes will further intensify the competition for freshwater resources. Currently, SAI is centered around predominantly rain-fed agricultural systems, often at a farm and plot scales. There has been increased attention to the improved role of agricultural water management (AWM) to address the daunting challenges of climate change, land degradation and food and nutritional insecurity in SSA. Nonetheless, the supporting frameworks and tools remain limited and do not connect the sustainability assessment and the development of intensification pathways (SIP) along multiple scales of the rainfed irrigation continuum. This paper reviews the gaps in concepts and practices of SAI and suggests a methodological framework to design context-specific and water-centered SIP for the SSA region. Accordingly, the proposed methodological framework demonstrates: (a) how to couple sustainability assessment methods to participatory SIPs design and adaptive management approach; (b) how contextualized sustainability domains and indicators can help in AWM centered SIP development; (c) the approaches to handle multiple scales and water-related indicators, the heterogeneity of biophysical and social settings when tailoring technology options to local contexts; and (d) the principles which enable the SIP designs to enable synergies and complementarities of SAI measures to reinforce the rainfed-irrigation continuum. This methodological framework allows researchers to integrate the sustainability assessment and SIP design, and guides policymakers and practitioners in planning, implementing and monitoring SAI initiatives (e.g., Framework for Irrigation Development and Agricultural Water Management in Africa) across multiple scales.

Designing Software Configurable Chips and SIPs using Chiplets and zGlue

Abstract zGlue Smart Fabric, an active silicon interposer, enables rapid development of Systems in Package (SiPs) and Chips using chiplet stacking in a modular style and software programmability. zGlue Smart Fabric works with off-the-shelf chiplets in known good die and wafer level chip scale packages format without dictating a footprint constraint on chiplets. This is achieved by making a fine pitch copper pillar micro-bump array on the surface that can conform to the chiplet ball map using a programable connectivity and power array built into zGlue's fabric. Connection to RF and sensitive analog signals are handled in RDL. Programmability of zGlue bumps also enable some repair and reconfigurability after manufacturing. The design process with zGlue includes usage of a cloud-based software design tool called ChipBuilder. This tool performs most conventional SiP design functions but more importantly it is used for creating soft and hard routes among IOs. ChipBuilder starts with a data representation of zGlue's Smart Fabric. A growing library of chiplet data has been encoded into the tool and is made available to the users of ChipBuilder via the cloud. Users select chiplets, enter design, perform IO planning, and route the design. With this modular IC design style, zGlue can handle high mix devices that are expected with the growth of connected smart devices everywhere.

Assignment of inter-die signals in a simplified wiring model for die-stacking SiP designs

Compared with traditional flow in IC designs, the assignment of the inter-die signals between different dies is an important stage in a die-stacking SiP design. In this paper, given a tolerant spacing rule between two inter-die signals, the crossing constraint between two inter-die signals can be firstly defined for the bonding wires in a die-stacking SiP design with a simplified wiring model [7]. Furthermore, based on the connection constraint on any inter-die signal, the capacity constraint on any assigned pad on dies and the crossing constraint between two inter-die signals, an integer linear programming-based (ILP-based) approach is proposed to assign all the inter-die signals to minimize the total wirelength in a die-stacking SiP design. Compared with Lin’s two-stage approach [4] for some tested examples without a tolerant spacing distance between two inter-die signals in an Euclidean wiring model, the experimental results show that our proposed ILP-based approach increases 4.5% of CPU time and reduces 6.2% of total wirelength to assign all the inter-die signals on the average. Besides that, compared with Yan’s iterative approach [6] for some tested examples without a tolerant spacing distance between two inter-die signals in an Euclidean wiring model, the experimental results show that our proposed ILP-based approach uses reasonable CPU time to reduce 5.3% of total wirelength to assign all the inter-die signals on the average. Compared with Lin’s modified two-stage approach and Yan’s modified iterative approach for some dense tested examples with a tolerant spacing distance between two inter-die signals in a simplified wiring model [7], the experimental results show that Lin’s modified two-stage approach only achieves 95.9% of the assignment ratio on the average, Yan’s modified iterative approach only achieves 96.6% of the assignment ratio on the average and our proposed ILP-based approach uses reasonable CPU time to achieve 100% of the assignment ratio.

Design and implementation of a 700–2,600 MHz RF SiP module for micro base station

In this paper, we present a complete 700---2,600 MHz RF SiP module for micro base station. This RF SiP design integrates transmitter, receiver, feedback module, ADC/DAC and CLK module. The module consists of two multi-layer organic substrates that are vertically stacked using BGA interconnections. With the integration of 33 chips and about 600 passive components, this RF SiP module retains small form factor and measures 5.25 cm × 5.25 cm × 0.7 cm. The RF input signal transmission path insertion loss is less than 0.34 dB and the return loss is less than ?14 dB at 2.6 GHz. Full load thermal simulation result indicates that each chip junction temperature is below 100 °C. We summarize the RF SiP module design, assembly and simulated thermal characteristics. The proposed RF SiP can generally be characterized by small size, low cost and short development cycle.

Renesas Technology halves SiP design time with “SiP Top-Down Design Environment”

Renesas Technology halves SiP design time with “SiP Top-Down Design Environment”

Wire Optimization for Multimedia SoC and SiP Designs

With advances in VLSI integration technology, a large number of hardware components can be integrated into a single chip. To provide the communication bandwidth for these components, existing bus-based interconnects often suffer from a large area occupied by a large number of bus signals. To address this issue, this paper proposes a new protocol for on-chip or in-package communication that is termed the system-on-chip network protocol (SNP). SNP uses a small number of signals that are shared by address, control, and data information. Additional three-bit phase signals are used to distinguish the different information transmitted through a single set of SNP signals. Two sets of identical SNP signals form a symmetric communication channel that allow a master-to-master type of communication between hardware components. The phase signals facilitate the reduction of the communication time with phase interleaving and phase omission-restoration among successive transactions. The efficiency of SNP is evaluated by a static performance analysis as well as by simulations with register-transfer level models of SNP components. Both the analysis and simulation results show that the communication time with SNP is approximately a half that of advanced microcontroller bus architecture advanced high-performance bus (AHB), although SNP has wires that are approximately three-fifths of AHB. MPEG-4 chips are implemented with both AHB and SNP, respectively, and it is observed from the MPEG-4 implementations that SNP requires less area for communication compared to AHB.

Design of a Low-Noise UWB Transceiver SiP

Ultrawideband (UWB) wireless communication systems are emerging as a promising solution for high-data-rate and short-distance wireless data transmission. In this article, we introduce a low-noise UWB transceiver SiP design for a compact implementation in a small mobile platform. The SiP's transmitter chip has a fully digital circuit implementation with a passive band-pass filter to meet a US Federal Communications Commission (FCC) regulation, and the receiver chip has a noncoherent architecture. To reduce noise generation and coupling in the densely integrated design, we considered signal integrity issues in the high-frequency channel and power integrity issues on the power distribution network (PDN) in the SiP substrate. Circuit-level and full-wave simulations confirm that the proposed design methodology improves signal integrity and power integrity. The UWB transceiver SiP consists of a fully digital transmitter system and a noncoherent receiver system.

Chip-package codesign flow for mixed-signal SiP designs

Design engineers are challenged with two separate entities: the chip and package designs. Because system-in-package integrates multiple dies into a package, design engineers should have a tool to easily combine the two entities. This article demonstrates a seven-die SiP design that implements a chip-and-package codesign platform using available EDA tools

Silicon sandwich [system-in-a-package

System-in-package looks to be an attractive option for projects that cannot justify a system-on-chip approach. SiP is a functional building block containing multiple die and possibly discretes in one semiconductor package. Its key advantage is adaptability, as the approach is appropriate for low or high volumes, and can handle mixed die and process technologies. SiP designs should also have lower development and non-recurring engineering (NRE) costs than SoC approaches. Among the disadvantages were the cumulative yields losses involved in linking the many devices that make up an SIP lower performance, and the availability or otherwise of known good die. System-in-package looks to be an attractive option for projects that cannot justify a system-on-chip approach. But there are many obstacles still to be overcome before it becomes mainstream, say people working with the technology.

The Need for a SiP Design and Test Infrastructure

Although successful and profitable applications have proven themselves in several market segments, significant challenges in system-in-package design and test remain for broader adoption.