Wire Optimization for Multimedia SoC and SiP Designs

Abstract

With advances in VLSI integration technology, a large number of hardware components can be integrated into a single chip. To provide the communication bandwidth for these components, existing bus-based interconnects often suffer from a large area occupied by a large number of bus signals. To address this issue, this paper proposes a new protocol for on-chip or in-package communication that is termed the system-on-chip network protocol (SNP). SNP uses a small number of signals that are shared by address, control, and data information. Additional three-bit phase signals are used to distinguish the different information transmitted through a single set of SNP signals. Two sets of identical SNP signals form a symmetric communication channel that allow a master-to-master type of communication between hardware components. The phase signals facilitate the reduction of the communication time with phase interleaving and phase omission-restoration among successive transactions. The efficiency of SNP is evaluated by a static performance analysis as well as by simulations with register-transfer level models of SNP components. Both the analysis and simulation results show that the communication time with SNP is approximately a half that of advanced microcontroller bus architecture advanced high-performance bus (AHB), although SNP has wires that are approximately three-fifths of AHB. MPEG-4 chips are implemented with both AHB and SNP, respectively, and it is observed from the MPEG-4 implementations that SNP requires less area for communication compared to AHB.