SiO2 Capping Layer Research Articles

Blue-green emitting microdisks using low-temperature-grown ZnO on patterned silicon substrates

Zinc oxide (ZnO) as an extremely bright emitter is an attractive material for photonic devices. However, devices made of epitaxially grown ZnO are difficult to fabricate due to the lack of selective etching processes. Here, we demonstrate that by a low-temperature growth process on pre-patterned silicon dioxide (SiO₂) microdisks (MDs) high quality ZnO resonators are created. The devices exhibit whispering gallery modes (WGMs) over the blue-green part of the visible spectrum with quality factors exceeding Q = 3500, which are among the highest values reported in this material system so far. By deposition of SiO₂ capping layers we find an enhanced coupling of the spontaneous emission from the active medium into the MDs, observed by sharp WGMs up to a radial quantum number of N = 3.

Conducting properties of nearly depleted ZnO nanowire UV sensors fabricated by dielectrophoresis

ZnO nanowires (NWs) with different radii (rNW) have been aligned between pre-patterned electrodes using dielectrophoresis (DEP) for the fabrication of high gain UV sensors. The DEP conditions (voltage amplitude and frequency) and electrode material, geometry and size were optimized to enhance the efficiency during the DEP process. To understand the alignment mechanism of the ZnO NWs, the dielectrophoretic force (FDEP) was analyzed as a function of the DEP conditions and NW dimensions. These studies showed that the DEP alignment process tends to trap NWs with a smaller radius. The effects of NW size on device performance were analyzed by means of I–V measurements in darkness and under illumination (200 nm < λ < 600 nm). In darkness, the NW resistance increases as rNW decreases due to the reduction of the conduction volume, until saturation is reached for rNW < 65 nm. On the other hand, the NW spectral photoresponse shows high values around 108 A W−1 (measured at 5 V and λ < 370 nm) and follows a linear trend as a function of the NW cross section. In addition, the cut-off wavelength depends on rNW, presenting a clear blue-shift for NWs with a lower radius (rNW < 50 nm). Transient photoresponse studies show that NWs with lower radii have longer rise times and shorter decay times mainly due to surface trapping effects. Regardless of NW size, passivation of the surface using a dielectric capping layer of SiO2 reduces the dynamic range of the photoresponse due to a strong increase of the dark current.

Silicon films with gallium-rich nanoinclusions: from superconductor to insulator

Si films sputter deposited on thermally oxidized Si are enriched with Ga by ion implantation through a SiO2 capping layer. The morphology and the electrical transport properties of these films are investigated after rapid thermal annealing. Amorphous, Ga-rich nanoinclusions are embedded in a nanocrystalline Si matrix. The metallic nanoinclusions become superconducting below 7 K. They form a random network of junctions to heavily doped Si crystallites. Small modifications of the junction properties, e.g. by annealing or current pulses, can dramatically change the electronic transport in the film. Ga-rich Si films show a wealth of low-temperature transport phenomena, which have been known until now only from granular metals or high-temperature superconductors: superconductor–insulator transition, quasi-reentrant superconductivity and current-controlled sheet resistance. The possibility to prepare and modify Ga-rich Si films with microelectronics-compatible technology makes them interesting for both fundamental research on transport phenomena in nanostructured, disordered superconductors as well as for the integration of superconducting circuits into Si devices.

Formation of silicon nanoparticles by a pressure induced nucleation mechanism

Formation of silicon nanoparticles (SiNPs) was achieved using excimer laser crystallization of an amorphous Si (a-Si) thin film using a SiO2 capping layer (C/L) with improved thin-film transistor (TFT) performance due to the enlarged grain size of polycrystalline Si (poly-Si). After laser irradiation of an a-Si thin film covered with C/L, fluctuation in the surface morphology of the C/L was observed above the critical laser energy density (Ecr) with the formation of SiNPs. The grain size of the poly-Si layer after crystallization increased abruptly at the same time. A non-uniform pressure distribution beneath the SiO2 C/L was proposed for the initiation of nucleation, which is named pressure induced nucleation (PIN) mechanism. Following nucleation, the release of latent heat made it difficult for the remnant liquid Si to solidify and the volume increased due to the density difference between the liquid and solid Si. Consequently, the pressure on the liquid Si caused SiNPs to sprout through the SiO2 C/L as grains grew from the low temperature to high temperature point. This study offers not only a simple method to fabricate SiNPs with controllable size/density but also larger grain size with lower laser energy density, which leads to higher TFT performance.

Contact Doping of Silicon Wafers and Nanostructures with Phosphine Oxide Monolayers

Contact doping method for the controlled surface doping of silicon wafers and nanometer scale structures is presented. The method, monolayer contact doping (MLCD), utilizes the formation of a dopant-containing monolayer on a donor substrate that is brought to contact and annealed with the interface or structure intended for doping. A unique feature of the MLCD method is that the monolayer used for doping is formed on a separate substrate (termed donor substrate), which is distinct from the interface intended for doping (termed acceptor substrate). The doping process is controlled by anneal conditions, details of the interface, and molecular precursor used for the formation of the dopant-containing monolayer. The MLCD process does not involve formation and removal of SiO(2) capping layer, allowing utilization of surface chemistry details for tuning and simplifying the doping process. Surface contact doping of intrinsic Si wafers (i-Si) and intrinsic silicon nanowires (i-SiNWs) is demonstrated and characterized. Nanowire devices were formed using the i-SiNW channel and contact doped using the MLCD process, yielding highly doped SiNWs. Kelvin probe force microscopy (KPFM) was used to measure the longitudinal dopant distribution of the SiNWs and demonstrated highly uniform distribution in comparison with in situ doped wires. The MLCD process was studied for i-Si substrates with native oxide and H-terminated surface for three types of phosphorus-containing molecules. Sheet resistance measurements reveal the dependency of the doping process on the details of the surface chemistry used and relation to the different chemical environments of the P═O group. Characterization of the thermal decomposition of several monolayer types formed on SiO(2) nanoparticles (NPs) using TGA and XPS provides insight regarding the role of phosphorus surface chemistry at the SiO(2) interface in the overall MLCD process. The new MLCD process presented here for controlled surface doping provides a simple yet highly versatile means for achieving postgrowth doping of nanometer scale structures and interfaces.

Rapid and non-destructive identification of graphene oxide thickness using white light contrast spectroscopy

By white light contrast spectroscopy, we have successfully identified number of graphene oxide (GO) layers (⩽10 layers) and obtained a new refractive index of GO sheets (⩽10 layers) of nGO=1.2–0.24i. For few layers (⩽10 layers) GO sheets, both the contrast at ∼580nm wavelength and the Raman intensity of G band linearly increase with the increase of the layer numbers. However, due to the laser induced heating effects and the requirement of a reference Raman spectrum in Raman spectroscopy measurements, contrast spectroscopy is non-destructive and more efficient. Simulations based on the Fresnel’s equations agree well with evolution of the contrast and G band intensity as a function of number of layers. The precise refractive index of GO obtained in this work can be widely used in further study of GO. Therefore, our experimental contrast values can be directly used as a standard to identify the thickness of GO on Si substrate with 300nm SiO2 capping layer, which paves a novelty way towards future fundamental research and applications of graphene-based materials.

Prevention of dewetting during annealing of FePt films for bit patterned media applications

We investigated different fabrication methods for (002) textured high anisotropy L10-FePt thin continuous films. While depositing at elevated temperature or post-annealing yields discontinuous or very rough films unsuitable for bit patterned media (BPM) fabrication, post-annealing with an additional SiO2 cap layer results in smooth continuous L10-FePt thin films that can be used for patterning. The SiO2 layer can be removed after annealing without significantly damaging the FePt, thus allowing additional deposition of lower anisotropy layers for forming exchange coupled composite or other layered BPM structures.

Mechanical constraint and release generates long, ordered horizontal pores in anodic alumina templates

We describe the formation of long, highly ordered arrays of planar oriented anodic aluminum oxide (AAO) pores during plane parallel anodization of thin aluminum ‘finger’ microstructures fabricated on thermally oxidized silicon substrates and capped with a silicon oxide layer. The pore morphology was found to be strongly influenced by mechanical constraint imposed by the oxide layers surrounding the Al fingers. Tractions induced by the SiO2 substrate and capping layer led to frustrated volume expansion and restricted oxide flow along the interface, with extrusion of oxide into the primary pore volume, leading to the formation of dendritic pore structures and meandering pore growth. However, partial relief of the constraint by a delaminating interfacial fracture, with its tip closely following the anodization front, led to pore growth that was highly ordered with regular, hexagonally packed arrays of straight horizontal pores up to 3 µm long. Detailed characterization of both straight and dendritic planar pores over a range of formation conditions using advanced microscopy techniques is reported, including volume reconstruction, enabling high quality 3D visualization of pore formation.

Horizontally aligned ZnO nanowire transistors using patterned graphene thin films

Here we report the directed growth of ZnO nanowires on multilayer graphene films (MGFs) without the use of metal seed materials. The ZnO source substance was diffused onto the MGF surface, where nanowires tended to grow in the high surface energy sites. This property was exploited to fabricate top-gate structural nanowire transistors with ZnO nanowires grown in the direction of the exposed sides of 6 × 4 μm patterned MGFs with a SiO2 capping layer. The devices showed an on-current of 160 nA, a threshold voltage of −2.27 V, an on-off current ratio of 3.98 × 105, and a field effect mobility of ∼41.32 cm2/V·s.

Low temperature formation of Si1 − x − yGexSny-on-insulator structures by using solid-phase mixing of Ge1 − zSnz/Si-on-insulator substrates

We proposed the low temperature formation technique of strain-relaxed Si1−x−yGexSny-on-insulator (SGTOI) structures. We found that the solid-phase reaction and the formation of single and uniform Si1−x−yGexSny layer on an insulator after annealing SiO2/Ge1−zSnz/SOI structures even at a temperature as low as 400°C. We characterized the crystalline structure of SGTOI, and investigated the effects of annealing, Sn incorporation, and a SiO2 cap layer on the solid-phase reaction between Ge1−zSnz and SOI layers. The solid-phase reaction is enhanced with a higher Sn content and a thicker SiO2 cap layer, and then Si1−x−yGexSny layers are more rapidly formed. The SGTOI layer exhibits very low mosaicity and have good crystallinity.

Silicon Surface Passivation by Thin Thermal Oxide/PECVD Layer Stack Systems

For the passivation of p-type silicon surfaces, we investigate layer systems consisting of a thin layer of thermally grown SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> and different dielectric capping layers deposited by means of plasma-enhanced chemical vapor deposition (PECVD). We find that the thermal SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> layer thickness strongly impacts the passivation quality and interface parameters of the stacks. Capacitance-voltage measurements reveal that for Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> and SiN <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</i> capping layers, an increased thermal SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> film thickness suppresses charge formation at the interface between SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> and the capping layer. Interface trap density and effective carrier lifetime data suggest that a certain thermal SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> thickness is required to achieve appropriate chemical passivation. The combination of a thin thermal SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> layer (~4 nm) and a PECVD-SiO <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</i> capping results in very low surface recombination velocities of a few centimeters per second, measured on p-type 1-Ω·cm float-zone silicon after contact firing and postmetallization annealing. The experimentally observed dependence of the surface recombination velocity on the fixed charge density, gate voltage, and injection density is reproduced very accurately by analytical calculations that use the measured interface trap density and total charge density at the Si/insulator interface. The model also includes additional recombination in the space charge region of inverted surfaces.

Local Doping of Silicon Using Nanoimprint Lithography and Molecular Monolayers

Micrometer-scale monolayer patterns of a phosphorus-containing molecular precursor are fabricated on nearly intrinsic Si(100) using nanoimprint lithography. The patterned sample is protected by a SiO2capping layer applied by electron beam evaporation and subjected to rapid thermal annealing (RTA) to diffuse the phosphorus dopant atoms into the bulk silicon locally.

Bias stress stability of zinc-tin-oxide thin-film transistors with Al2O3 gate dielectrics

The bias stability of zinc-tin-oxide (ZTO) thin-film transistors (TFTs) with either Al2O3 gate dielectrics deposited via atomic layer deposition (ALD) or SiO2 gate dielectrics deposited via plasma-enhanced chemical vapor deposition (PECVD) was compared. Both device types showed incremental mobility ≥11 cm2/V s, subthreshold slopes &amp;lt;0.4 V/dec, and ION/IOFF ratios of ∼107. During repeated ID-VGS sweeping, both device types showed positive parallel shift of the turn-on voltage (VON) without significant degradation of subthreshold slope or mobility, consistent with electron trapping without creation of new traps. A smaller VON shift was observed in the SiO2/ZTO devices. In an effort to improve the bias stress stability of the Al2O3/ZTO devices, the impact of ALD temperature, plasma exposure of the Al2O3, and the addition of an interfacial PECVD SiO2 capping layer were investigated. The positive bias stress stability of the Al2O3/ZTO TFTs was found to be relatively unaffected by the Al2O3 ALD temperature, degraded with plasma exposure, and improved by the addition of a thin (∼3 nm) PECVD SiO2 interfacial layer between the Al2O3 dielectric and the ZTO channel. These results point to the vicinity of the Al2O3/ZTO interface as the dominant source of charge trapping.

How thick SiO2 cap layer is needed to achieve strong visible photoluminescence from SiO2-buffered SiNx films?

The effect of a SiO(2) nanolayer and annealing temperature on the UV/visible room-temperature photoluminescence (PL) from SiN(x) films synthesized by rf magnetron sputtering is studied. The PL intensity can be maximized when the SiO(2) layer is 5-10 nm thick at 800 degrees C annealing temperature and only 2 nm at 1000 degrees C. A composition-structure-property analysis reveals that the PL intensity is directly related to both the surface chemical states and the content of the Si-0 and Si-N bonds in the SiN(x), films. These results are relevant for the development of advanced optoelectronic and photonic emitters and sensors. (C) 2010 Elsevier B.V. All rights reserved.

Investigation of SiO2 Cap for Al Implant Activation in 4H-SiC

AbstractThe effect of using SiO2 capping layer during Al implant activation anneal on the performance of 4H-SiC P-i-N diodes has been investigated. Two sets of 4H-SiC pin diode samples, one with SiO2 cap and another with graphite cap, were annealed under high temperatures of 1500°C for activation after Al implantation at 650°C to form the p-type active region and the JTE region. The surface stoichiometry of annealed SiC was examined by x-ray photoelectron spectroscopy (XPS). Various material and device parameters including surface roughness, sheet resistance, minimum forward leakage current and maximum breakdown voltage have been extracted for comparison. The results show that SiO2 cap effectively protects the SiC surface during high temperature implant annealing.

Magnetization Reversal Mechanism and Microstructure Refinement of the FePt (001) Nanogranular Films With SiO$_{2}$ Capping Layer

Ordered FePt continuous thin films with an amorphous SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> single capping layer have been fabricated on MgO (001) single-crystal substrates by the electron beam deposition technique at 400degC in order to investigate the effects of SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> capping layer on microstructure and magnetic reversal process of the FePt (001) thin films. The formation of nanogranular-like FePt films was directly obtained with this process due to the interpenetration of SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> which has a lower surface energy than that of pure Fe or Pt. Studies of angular dependent coercivity show a tendency of a domain-wall motion weaken towards rotation of reverse-domain type upon thickness of SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> capping layer on the FePt thin films. The intergrain interaction was confirmed from the Kelly-Henkel (delta <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">M</i> ) plot that indicated the strong exchange coupling between neighboring grains in the FePt continuous films without SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> capping layer. On the other hand, negative delta <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">M</i> value was obtained when the FePt films with SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> capping layer, indicating the SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> capping layer, can lead to the reduction of intergrain exchange coupling thus presence of dipole interaction in the SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /FePt nanocomposite thin film structures.

New solid‐phase crystallization of amorphous silicon by selective area heating

A new crystallization method for amorphous silicon, called selective area heating (SAH), was proposed. The purpose of SAH is to improve the reliability of amorphous silicon films with extremely low thermal budgets to the glass substrate. The crystallization time shortened from that of the conventional solid‐phase crystallization method. An isolated thin heater for SAH was fabricated on a quartz substrate with a Pt layer. To investigate the crystalline properties, Raman scattering spectra were used. The crystalline transverse optic phonon peak was at about 519 cm‐1, which shows that the films were crystallized. The effect of the crystallization time on the varying thickness of the SiO2 films was investigated. The crystallization area in the 400nm‐thick SiO2 film was larger than those of the SiO2 films with other thicknesses after SAH at 16 W for 2 min. The results show that a SiO2 capping layer acts as storage layer for thermal energy. SAH is thus suggested as a new crystallization method for large‐area electronic device applications.

Crystallisation of Amorphous Germanium Thin Films

By combining cross-sectional transmission and scanning electron microscopy with Raman scattering we have investigated the mechanism of nanocrystal formation in ultrathin amorphous SiO2/Ge/SiO2 trilayers grown by e-beam evaporation as a function of annealing temperature and a-Ge layer thickness. We observe that with decreasing a-Ge thickness the amorphous-to-crystalline (a-to-c) transition occurs at considerably higher temperatures, even avoiding crystallisation for very thin films below 2 nm thickness. Furthermore, we demonstrate that the formation of Ge nanocrystals by annealing at around 900 degrees C takes place driven by a liquid-mediated mechanism. As indicated by the observed microstructure, the metallic liquid film dewets from the surface forming droplets that upon cooling and under the influence of the SiO2 capping layer, solidify into barrel-type nanocrystals.

AlInGaN 310 nm ultraviolet metal-insulator-semiconductor sensors with photo-chemical-vapor-deposition SiO2 cap layers

Al0.25In0.04Ga0.71N 310 nm near solar blind ultraviolet (UV) metal-insulator-semiconductor (MIS) sensors with different SiO2 cap layer thickness were successfully fabricated. With appropriate SiO2 layer thickness, the dark current of AlInGaN sensors was notably suppressed from 1.88 × 10−6 to 1.91 × 10−9 A, and the photo-generated carriers still could reach the electrodes by tunneling through the thin SiO2 layer under the illumination. It could be clearly seen that cut-off occurred at around 300/310 nm while the responses above the bandgap were flat.

Epitaxial 3C-SiC nanocrystal formation at the SiO2/Si interface by combined carbon implantation and annealing in CO atmosphere

High quality 3C-SiC nanocrystallites were epitaxially formed on (100) Si wafers covered by a 150 nm thick SiO2 capping layer after low dose carbon implantation and high temperature annealing in CO atmosphere. Carbon implantation is used to introduce nucleation sites by forming silicon-carbon clusters at the SiO2/Si interface acting as nucleation sites for the growth of 3C-SiC nanocrystallites. The formation of the nucleation clusters as well as the morphology, the size, and the density of the nanocrystals were systematically studied by conventional and high resolution transmission electron microscopy. The nanocrystallites were developed following two different modes of growth: The first develops facets along the ⟨100⟩ crystallographic direction giving tetragonal grains and the second facets along the ⟨110⟩ direction resulting in elongated nanocrystallites. The formation mechanism of the nanocrystallites and the strain related with them are also discussed.