Bias stress stability of zinc-tin-oxide thin-film transistors with Al2O3 gate dielectrics

Abstract

The bias stability of zinc-tin-oxide (ZTO) thin-film transistors (TFTs) with either Al2O3 gate dielectrics deposited via atomic layer deposition (ALD) or SiO2 gate dielectrics deposited via plasma-enhanced chemical vapor deposition (PECVD) was compared. Both device types showed incremental mobility ≥11 cm2/V s, subthreshold slopes <0.4 V/dec, and ION/IOFF ratios of ∼107. During repeated ID-VGS sweeping, both device types showed positive parallel shift of the turn-on voltage (VON) without significant degradation of subthreshold slope or mobility, consistent with electron trapping without creation of new traps. A smaller VON shift was observed in the SiO2/ZTO devices. In an effort to improve the bias stress stability of the Al2O3/ZTO devices, the impact of ALD temperature, plasma exposure of the Al2O3, and the addition of an interfacial PECVD SiO2 capping layer were investigated. The positive bias stress stability of the Al2O3/ZTO TFTs was found to be relatively unaffected by the Al2O3 ALD temperature, degraded with plasma exposure, and improved by the addition of a thin (∼3 nm) PECVD SiO2 interfacial layer between the Al2O3 dielectric and the ZTO channel. These results point to the vicinity of the Al2O3/ZTO interface as the dominant source of charge trapping.