Single Transistor Research Articles

Triboelectric-potential configurable MoTe2 homojunction for photovoltaic device and logic circuits

Reconfigurable devices based on two-dimensional materials are considered as one of the ways to extend Moore's Law. However, most reconfigurable devices use a gate voltage to dope the channel electrostatically, and the continuously applied gate voltage poses the problem of high device power consumption. Here, for the first time, we propose a tribotronic reconfigurable MoTe2 field effect transistor, where the power consumption of the device is greatly reduced by using triboelectric potentials generated by external mechanical operations instead of applying gate voltages. The drain current noise spectral density test proves that no additional current noise interferes with the output current during mechanical operation. Mechanical operation allows facile modulation of four different channel polarities (n-n, p-p, p-n, and n-p) in a single transistor. We demonstrate the potential application of a tribotronic p-n diode for photovoltaic device. The logic circuit composed of two tribotronic reconfigurable transistors realizes the logic functions of inverter, AND gate, and OR gate. Our device extends tribotronic logic and demonstrates great potential for human-machine interaction, intelligent sensors, and wearable devices.

Enhancing Memory Window Efficiency of Ferroelectric Transistor for Neuromorphic Computing via Two‐Dimensional Materials Integration

AbstractIn‐memory computing, particularly neuromorphic computing, has emerged as a promising solution to overcome the energy and time‐consuming challenges associated with the von Neumann architecture. The ferroelectric field‐effect transistor (FeFET) technology, with its fast and energy‐efficient switching and nonvolatile memory, is a potential candidate for enabling both computing and memory within a single transistor. In this study, the capabilities of an integrated ferroelectric HfO2and 2D MoS2channel FeFET in achieving high‐performance 4‐bit per cell memory with low variation and power consumption synapses, while retaining the ability to implement diverse learning rules, are demonstrated. Notably, this device accurately recognizes MNIST handwritten digits with over 94% accuracy using online training mode. These results highlight the potential of FeFET‐based in‐memory computing for future neuromorphic computing applications.

CNTFET-based Data Independent Power Efficient and Robust 8T SRAM Cell

A new carbon nano-tube field-effect transistors (CNTFETs) based Power Efficient and Robust 8T (PER-8T) SRAM cell is proposed to reduce sub-threshold leakage currents, data dependency by improving RBL swing due to which RSNM is improved. Leakage power is reduced by using only single pull-up transistor with High V t in storage latch. Half-select issue is eliminated since proposed work uses de-coupled read port. This CNTFET based proposed PER-8T cell is analysed for performance parameters like power, delay and stability and compared to 8T SRAM cells at 45 nm technology. All simulations are performed at supply voltage of 0.9 V considering Stanford Virtual Source CNTFET(VS-CNTFET) model. It shows that RSNM and WSNM are improved by 12.07%, 14.85%, 56% and 46.46%, 20.39%, 66.05% compared to single ended 8T SRAM cells available in recent literature. Effects of VS-CNTFET parameters such as dielectric material, temperature, oxide thickness and carbon nano tube diameter values on hold power is analysed and best values are considered. The cadence tool is used for measuring all design metrics at room temperature of 25 °C.

Synaptic Transistor Arrays Based on PVA/Lignin Composite Electrolyte Films

With the development of information society, the traditional von Neumann-based computing system is facing significant challenges. The search for an intelligent computing system similar to the biological brain would be a very effective solution to the present-day von Neumann bottleneck. Electrolyte-gated transistors (EGTs) have received much attention because they can simulate biological synaptic behavior very effectively. However, large-scale EGTs arrays are still lacking because most of the existing reported EGTs use organic or liquid electrolytes, which poses a significant challenge to the current production methods for manufacturing integration using photolithography. Although synaptic transistor arrays using solid-state electrolytes have the potential for large-scale fabrication, the power consumption required for individual transistors is relatively high. In this work, an electrolyte transistor array (10 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times$</tex-math> </inline-formula> 10) fabricated by the photolithography process was successfully proposed, where the individual transistors in the array used a composite polyvinyl alcohol (PVA)/lignin electrolyte as the gate dielectric layer. The switching ratio of a single transistor can reach 106, and the maximum gate leakage current is 43.96 pA in the voltage range of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$-$</tex-math> </inline-formula> 3 to 3 V. In addition, the synaptic properties, such as excitatory postsynaptic current (EPSC) and paired-pulse-facilitation (PPF), were successfully achieved. When the pulse duration is 100 ms, the energy consumption of the transistor is 0.63 nJ. The number’s dynamic memory and forgetting functions were also successfully simulated by the artificial synaptic transistor array. This work will provide a useful idea for large-scale array integration of EGTs using organic and liquid electrolytes as gate dielectric layers.

Study of Self Heating Effect in the wake of complete and partial bottom dielectric insertion under 5 nm Stacked Nanosheet Transistor

Beyond 7 nm technology nodes, a Stacked Nanosheet Field Effect Transistor (SNT) is a potential candidate to continue device scaling due to its higher ON/OFF current ratio and less Short Channel Effect than FinFET. However, its gate all-around structure with low thermal conductive HiK oxide material exacerbates the Self-Heating Effect (SHE) issue in the SNT. Further, a dielectric inserted beneath SNT to reduce leakage current disrupts the primary heat flow path through the substrate, aggravating the Self Heating Effect (SHE). This study focuses on exploring the thermal aspect of the SNT with partial and complete dielectric insertion under the device from a performance and reliability perspective. A 3D electrothermal analysis has been performed using Synopsys TCAD tool. The effect of partial and complete dielectric insertion under the device on lattice temperature was investigated in the case of single and double-stack nanosheet transistors. The effects of dielectric insertion on channel and substrate temperature were analyzed. Its variation with width, extension length, interface thermal resistance, and the number of sheets and stack pitch of SNT are discussed. Sheet-dependent heat flow through the substrate and source/drain contact explained for different types of SNT structures and its effect on device performance and reliability discussed. To discuss the effect of multiple parameters variation on the lattice temperature of the device, Analysis of Variance (ANOVA) method was used. It was found that complete dielectric insertion leads to a severe heating issue in the SNT compared to partial and without dielectric insertion.

Reconfigurable Artificial Synapse Based on Ambipolar Floating Gate Memory.

Artificial synapse networks capable of massively parallel computing and mimicking biological neural networks can potentially improve the processing efficiency of existing information technologies. Semiconductor devices functioning as excitatory and inhibitory synapses are crucial for developing intelligence systems, such as traffic control systems. However, achieving reconfigurability between two working modes (inhibitory and excitatory) and bilingual synaptic behavior in a single transistor remains challenging. This study successfully mimics a bilingual synaptic response using an artificial synapse based on an ambipolar floating gate memory comprising tungsten selenide (WSe2)/hexagonal boron nitride (h-BN)/ molybdenum telluride (MoTe2). In this WSe2/h-BN/MoTe2 structure, ambipolar semiconductors WSe2 and MoTe2 are inserted as channel and floating gates, respectively, and h-BN serves as the tunneling barrier layer. Using either positive or negative pulse amplitude modulations at the control gate, this device with bipolar channel conduction produced eight distinct resistance states. Based on this, we experimentally projected that we could achieve 490 memory states (210 hole-resistance states + 280 electron-resistance states). Using the bipolar charge transport and multistorage states of WSe2/h-BN/MoTe2 floating gate memory, we mimicked reconfigurable excitatory and inhibitory synaptic plasticity in a single device. Furthermore, the convolution neural network formed by these synaptic devices can recognize handwritten digits with an accuracy of >92%. This study identifies the unique properties of heterostructure devices based on two-dimensional materials as well as predicts their applicability in advanced recognition of neuromorphic computing.

Reconfigurable signal modulation in a ferroelectric tunnel field-effect transistor

Reconfigurable transistors are an emerging device technology adding new functionalities while lowering the circuit architecture complexity. However, most investigations focus on digital applications. Here, we demonstrate a single vertical nanowire ferroelectric tunnel field-effect transistor (ferro-TFET) that can modulate an input signal with diverse modes including signal transmission, phase shift, frequency doubling, and mixing with significant suppression of undesired harmonics for reconfigurable analogue applications. We realize this by a heterostructure design in which a gate/source overlapped channel enables nearly perfect parabolic transfer characteristics with robust negative transconductance. By using a ferroelectric gate oxide, our ferro-TFET is non-volatilely reconfigurable, enabling various modes of signal modulation. The ferro-TFET shows merits of reconfigurability, reduced footprint, and low supply voltage for signal modulation. This work provides the possibility for monolithic integration of both steep-slope TFETs and reconfigurable ferro-TFETs towards high-density, energy-efficient, and multifunctional digital/analogue hybrid circuits.

Monitoring of histamine-induced calcium channel activity of a single cell using semiconducting carbon nanotube transistors

A method using transistors based on semiconducting carbon nanotubes were developed for the real-time monitoring of the electrophysiological responses of individual cells to histamine stimulation. Transistors with one or three floating electrodes were utilized to evaluate histamine-induced Ca2+ influx into Hela cells via the recording of the conductance changes of the transistors. The Ca2+ influx resulted from the activation of histamine H1 receptors embedded on the cell membranes by histamine, which generated a temporary negative potential at the gap between the cell and the transistor. Moreover, the antihistamine effects of chlorpheniramine on histamine-induced Ca2+ influx were also investigated by using a transistor including three floating electrodes. Especially, only a single transistor was applied to repeat the measurements of the responses of multiple Hela cells pretreated with chlorpheniramine to histamine stimulation. This allows us to acquire data without being suffered from device-to-device variations, implying our method would be a simple but powerful method for applications of nanoscale biosensors to electrophysiological studies.

Single molecule photonic transistor and router through plasmonic nanocavity

Single molecule photonic transistor and router through plasmonic nanocavity

36.1: Invited Paper: Innovations in Thin Film Electronics for the New Generation of Displays

Improvements in semiconductor materials carried Moore's Law into the 1990s, where device geometries and limits in materials performance drove the need for fundamental innovation at the materials and structural levels of MOSFETs. The display industry has reached a similar point the need for fundamental innovation at the materials and structural levels of thin film transistors. Successful transition to a higher plateau of thin film device technology enables a new inflection point in the use of displays just as the FinFET was the foundation for an inflection point in the use of microprocessors.This paper provides an overview of two thin film technology innovations offering promise as the next two plateaus in the evolution of thin film integrated circuit manufacturing: achieving bulk accumulation in single gate metal oxide semiconductor thin film transistors, and semiconductor less quantum tunneling. Linked through a single core materials set based on strong yet flexible amorphous metals, these two innovations create a roadmap simplifying the manufacturing of high image quality, low power consumption displays on glass and plastic.

Ferroelectric-gate tunnel field-effect transistor one-transistor ternary contents addressable memory

In the era of ‘big data’, the von Neumann architecture has significant energy consumption and latency penalties for data transfer between memory and processor. However, ternary content addressable memories (TCAMs) enable fast and energy-efficient operation by performing a parallel search for given data and returning information about whether it matches. In this study, a single transistor (1T) ferroelectric-gate tunnel FET (FeTFET) was introduced for TCAM operations, and its functionality was verified through technology computer-aided design (TCAD) simulations. The FeTFET has intrinsic directional currents due to its unique p–i–n structure. Also, the transfer curve of the FeTFET can be shifted in both directions depending on the polarization state of the ferroelectric material. By combining these properties of the FeTFET, it was confirmed that stable search operations can be performed for stored logic states. Thus, compared to conventional TCAM cell that use two or more transistors, it is expected that the proposed 1T-TCAM cell can store and search more bits in the same area.

Self‐Curable Synaptic Ferroelectric FET Arrays for Neuromorphic Convolutional Neural Network

With the recently increasing prevalence of deep learning, both academia and industry exhibit substantial interest in neuromorphic computing, which mimics the functional and structural features of the human brain. To realize neuromorphic computing, an energy-efficient and reliable artificial synapse must be developed. In this study, the synaptic ferroelectric field-effect-transistor (FeFET) array is fabricated as a component of a neuromorphic convolutional neural network. Beyond the single transistor level, the long-term potentiation and depression of synaptic weights are achieved at the array level, and a successful program-inhibiting operation is demonstrated in the synaptic array, achieving a learning accuracy of 79.84% on the Canadian Institute for Advanced Research (CIFAR)-10 dataset. Furthermore, an efficient self-curing method is proposed to improve the endurance of the FeFET array by tenfold, utilizing the punch-through current inherent to the device. Low-frequency noise spectroscopy is employed to quantitatively evaluate the curing efficiency of the proposed self-curing method. The results of this study provide a method to fabricate and operate reliable synaptic FeFET arrays, thereby paving the way for further development of ferroelectric-based neuromorphic computing.

A Novel Word Line Driver Circuit for Compute-in-Memory Based on the Floating Gate Devices

In floating gate compute-in-memory (CIM) chips, due to the gate equivalent capacitance of the large-scale array and the parasitic capacitance of the long-distance transmission wire, it is difficult to balance the switching speed and area of the word line driver circuit (WLDC). The difference among multiple voltage domains required for floating gate CIM devices has also far exceeded the withstand voltage range of a single transistor in the WLDC. This paper proposes a novel WLDC based on the working principle of the CIM array. A multi-level pre-processing voltage control method is adopted to carry out an optional hierarchical transmission of multiple high voltages, significantly reducing the propagation delay. The proposed WLDC is based on the Wilson current mirror structure, which substantially reduces the physical design area. The simulation results show that the circuit can convert a 1.2 V low-voltage domain input signal with a frequency of 10 MHz into a high-voltage domain output voltage, and the output voltage range of a single WLDC can reach −10 V to 10 V. With a capacitive load within 5 pF, the transmission delay is less than 10 ns. The layout area is 594.88 µm2, which is suitable for a large-scale CIM array.

Expanding the Set of Three-Input Logic Functions in Inverted T-Shaped TFETs

Three-input logic primitives show high efficiency in logic synthesis compared to traditional two-input logic, which encourages researchers to implement three-input logic gates with emerging nanotechnologies. This paper demonstrates a compact implementation of three-input monotone logic gates based on the inverted T-shaped TFET. Firstly, based on the gate coupling mechanism in the novel inverted T channel, the BTBT current can be suppressed in the vertical or horizontal region to achieve the channel strobe. Therefore, the typical three-input monotone logic functions, Majority, OrAnd, and AndOr, are successfully implemented on a single transistor. Then, a simplified potential model describing gate coupling is established to describe the impact of key device parameters on the logic behavior. Combined with TCAD simulation, the design rules of devices with different logic functions are given. Finally, a series of three-input monotonic logic gates are designed and verified. The results show that the use of the proposed TFETs can effectively save the number of transistors in the three-input logic gate, which indicates that the three-input TFET is a compact and flexible candidate for three-input logic gates.

Origin of electrically induced defects in monolayer MoS2 grown by chemical vapor deposition

Defects in MoS2 play substantial role in determining the performance of MoS2-based field-effect transistors. Typically, growth/synthesis process conditions determine the type and concentration of defects. Here, we show that defects are also introduced by prolonged operation of single crystal chemical vapor deposition-grown monolayer MoS2 transistors which hinder the overall performance. Depending on the electrical stress conditions, these defects result in threshold voltage instabilities, enhanced channel conductance, improved screening of charged impurity scattering sites and possibly better thermal management in MoS2 transistors. It turns out that a piezoelectric response in MoS2 leads to permanent change in the material’s molecular configuration thereby causing other effects like suppressed hopping transport within the channel, increased free electron concentration, prominent metal-insulator transition and reduction in channel potential with or without increasing sulfur vacancy concentration. As these defects are progressively introduced in the channel, the thermal dissipation capability of our MoS2 transistors improved due to enhanced channel-dielectric coupling. Such variations in the device performance due to spontaneous response to high electric field trigger a need to reconsider supply voltage requirements of MoS2-based electronic circuits for low-power logic applications.

Nanowire single-crystal grain and single grain boundary silicon field effect transistors for direct electrical characterization of grain boundaries

Single crystal grain (s-G) and single grain boundary (s-GB) Si field effect transistors (FETs) were investigated for direct measurement of the electrical activity of GBs. Ultrahigh-performance nanowire s-G FET with 1360 cm2V−1s−1 electron field-effect mobility (μ ef) was achieved on a transparent substrate. The significant difference of μ ef values between nanowire and microwire FETs proved that uniaxial tensile strain typically contributed to μ ef enhancement in nanowire FETs. Longitudinal GBs typically increased the leakage current and S factor due to a large donor concentration. The donor concentration generated by Σ3 and other CSL-type s-GBs was estimated.

Artificial Multisensory Neuron with a Single Transistor for Multimodal Perception through Hybrid Visual and Thermal Sensing.

An artificial multisensory device applicable to in-sensor computing is demonstrated with a single-transistor neuron (1T-neuron) for multimodal perception. It simultaneously receives two sensing signals from visual and thermal stimuli. The 1T-neuron transforms these signals into electrical signals in the form of spiking and then fires them for a spiking neural network at the same time. This feature makes it feasible to realize input neurons for multimodal sensing. Visual and thermal sensing is achieved due to the inherent optical and thermal behaviors of the 1T-neuron. To demonstrate a neuromorphic multimodal sensing system with the artificial multisensory 1T-neuron, fingerprint recognition, widely used for biometric security, is implemented. Owing to the simultaneous sensing of heat as well as light, the proposed fingerprint recognition system composed of multisensory 1T-neurons not only identifies a genuine pattern but also judges whether or not it is forged.

A novel dual-BJT avalanche pulse generator with mixer effect

AbstractThis paper presents a novel, simple, and efficient pulse generation technique using BJTs in avalanche mode with mixer effect. The presented design is an improved version of the basic single transistor avalanche pulse generator, and it composes of two identical pulse generators that drive a common 50-Ω load resistor at the output. The output signal exhibits wider bandwidth and narrower pulsewidth, compared to the basic single transistor circuit. The presented pulse generator also provides increased power output without using any power amplifier, and can be used in ground-penetrating radar and ultra-wideband communication systems.

Graphene FETs with high and low mobilities have universal temperature-dependent properties

We use phenomenological modelling and detailed experimental studies of charge carrier transport to investigate the dependence of the electrical resistivity, ρ, on gate voltage, V g , for a series of monolayer graphene field effect transistors with mobilities, μ, ranging between 5000 and 250 000 cm2 V−1 s−1 at low-temperature. Our measurements over a wide range of temperatures from 4 to 400 K can be fitted by the universal relation for all devices, where is the resistivity maximum at the neutrality point and δn is an ‘uncertainty’ in the bipolar carrier density, given by the full width at half maximum of the resistivity peak expressed in terms of carrier density, n. This relation is consistent with thermal broadening of the carrier distribution and the presence of the disordered potential landscape consisting of so-called electron–hole puddles near the Dirac point. To demonstrate its utility, we combine this relation with temperature-dependent linearised Boltzmann transport calculations that include the effect of optical phonon scattering. This approach demonstrates the similarity in the temperature-dependent behaviour of carriers in different types of single layer graphene transistors with widely differing carrier mobilities. It can also account for the relative stability, over a wide temperature range, of the measured carrier mobility of each device.

A new dithieno[3,2-b:2',3'-d]thiophene derivative for high performance single crystal organic field-effect transistors and UV-sensitive phototransistors.

Organic phototransistors (OPTs), as the basic unit for organic image sensors, are emerging as one of the most promising light signal detectors. High performance UV-sensitive phototransistors are highly desired for the detection of UV light. Herein, by introducing the anthracene group to the 2,6-positions of dithieno[3,2-b:2',3'-d]thiophene, we designed and synthesized a new dithieno[3,2-b:2',3'-d]thiophene derivative, 2,6-di(anthracen-2-yl)dithieno[3,2-b:2',3'-d]thiophene (2,6-DADTT). The single crystal structure of 2,6-DADTT presents classical herringbone packing with multiple intermolecular interactions, including S⋯S (3.470 Å), S⋯C (3.304 Å, 3.391 Å, 3.394 Å) and C-H⋯π (2.763 Å, 2.822 Å, 2.846 Å, 2.865 Å, 2.885 Å, 2.890 Å) contacts. Single crystal organic field-effect transistors (SC-OFETs) based on 2,6-DADTT reach a highest mobility of 1.26 cm2 V-1 s-1 and an average mobility of 0.706 cm2 V-1 s-1. 2,6-DADTT-based single crystal organic phototransistors (OPTs) demonstrate photosensitivity (P) of 2.49 × 106, photoresponsivity (R) of 6.84 × 103 A W-1 and ultrahigh detectivity (D*) of 4.70 × 1016 Jones to UV light, which are among the best figures of merit for UV-sensitive OPTs. These excellent comprehensive performances indicate its good application prospects in integrated optoelectronics.