Single Instruction Research Articles

Parsing Millions of DNS Records Per Second

ABSTRACTObjectivesTo enhance the throughput of DNS parsing by addressing the computational expense of processing large plain text DNS zone files.To specifically increase the speed of parsing DNS zone files compared to existing state‐of‐the‐art parsers.MethodDevelopment of a new approach named simdzone for DNS parsing.Utilization of data parallelism through Single Instruction Multiple Data (SIMD) instructions available on modern processors to accelerate parsing operations.ResultThe simdzone approach significantly increased parsing speeds, being several times faster than the parsers in Knot DNS and NLnet Labs' Name Server Daemon (NSD).The software library developed from this approach was integrated into NSD, replacing its previous parser.ConclusionThe implementation of SIMD‐based data parallelism in DNS parsing provides a substantial performance improvement, making it a viable solution for handling large DNS zone files more efficiently. This not only reduces processing time but also enhances the overall functionality of DNS services.

Optimization of SM2 Algorithm Based on Polynomial Segmentation and Parallel Computing

The SM2 public key cryptographic algorithm is widely utilized for secure communication and data protection due to its strong security and compact key size. However, the intensive large integer operations it requires pose significant computational challenges, which can limit the performance of Internet of Things (IoT) terminal devices. This paper introduces an optimized implementation of the SM2 algorithm specifically designed for IoT contexts. By segmenting large integers as polynomials within a modified Montgomery modular multiplication algorithm, the proposed method enables parallel modular multiplication and reduction, thus addressing storage constraints and reducing computational redundancy. For scalar multiplication, a Co-Z Montgomery ladder algorithm is employed alongside Single Instruction Multiple Data (SIMD) instructions to enhance parallelism, significantly improving efficiency. Experimental results demonstrate that the proposed scheme reduces the computation time for the SM2 algorithm’s digital signature by approximately 20% and enhances data encryption and decryption efficiency by about 15% over existing methods, marking a substantial performance gain for IoT applications.

SAMFL: Secure Aggregation Mechanism for Federated Learning with Byzantine-robustness by functional encryption

Federated learning (FL) enables collaborative model training without sharing private data, thereby potentially meeting the growing demand for data privacy protection. Despite its potentials, FL also poses challenges in achieving privacy-preservation and Byzantine-robustness when handling sensitive data. To address these challenges, we present a novel Secure Aggregation Mechanism for Federated Learning with Byzantine-Robustness by Functional Encryption (SAMFL). Our approach designs a novel dual-decryption multi-input functional encryption (DD-MIFE) scheme, which enables efficient computation of cosine similarities and aggregation of encrypted gradients through a single ciphertext. This innovative scheme allows for dual decryption, producing distinct results based on different keys, while maintaining high efficiency. We further propose TF-Init, integrating DD-MIFE with Truth Discovery (TD) to eliminate the reliance on a root dataset. Additionally, we devise a secure cosine similarity calculation aggregation protocol (SC2AP) using DD-MIFE, ensuring privacy-preserving and Byzantine-robust FL secure aggregation. To enhance FL efficiency, we employ single instruction multiple data (SIMD) to parallelize encryption and decryption processes. Concurrently, to preserve accuracy, we incorporate differential privacy (DP) with selective clipping of model layers within the FL framework. Finally, we integrate TF-Init, SC2AP, SIMD, and DP to construct SAMFL. Extensive experiments demonstrate that SAMFL successfully defends against both inference attacks and poisoning attacks, while improving efficiency and accuracy compared to existing methods. SAMFL provides a comprehensive integrated solution for FL with efficiency, accuracy, privacy-preservation, and robustness.

Scalar and vectorized implementations of the density functional theory via Geant4 and GeantV project

In this paper, we present the implementation of the Density Functional Theory (DFT) method using the Geant4-DNA framework in the Single Instruction Single Data (SISD) mode. Furthermore, this implementation is improved in terms of execution time within the GeantV project with vectorization techniques such as Single Instruction Multiple Data (SIMD). Within this framework, a set of SIMD strategies in molecular calculation algorithms such as one-electron operators, two-electron operator, quadrature grids, and functionals, was implemented using the VecCore library. The applications developed in this work implement two DFT functionals, the Local Density Approximation (LDA) and the General Gradient Approximation (GGA), to approximate the molecular ground-state energies of small molecules and amino acids. To assess the performance of the implementations, a standard test simulation was performed in multiple CPU platforms. The SIMD vectorization strategy significantly accelerates DFT calculations, leading to time ratios ranging from 1.6 to 5.4 in either individual steps or entire implementations when compared with the scalar process within Geant4.

Design of Low Power Control Unit for RISC-V Processor Core

This research work focuses on the development of a low-power decode logic for a RISC-V processor core with specifications. The goal is to create a controller that performs all six groups of instruction formats outlined in the RV32I Base Integer Instruction Set. The control unit is designed to decode a total of 13 instruction sets, allowing for a comprehensive range of operations. A single instruction pipeline approach is implemented in the design to optimize performance. The synthesis of the design is carried out using the 32 nm standard library, resulting in a maximum operating frequency of 666.67 MHz. To further enhance power efficiency, clock gating techniques are employed, leading to a reduction in power consumption by 18.72 % from 112.15 µW to 91.45 µW. Additionally, the layout of the design is optimized, resulting in an area of 354.74 mm2. The successful development of this low-power decode logic demonstrates its potential for integration into larger RISC-V processor cores. Future enhancements can include expanding the instruction decoding capability to encompass the full range of 47 instructions in the RV32I Base Integer Instruction Set, as well as exploring additional pipeline stages to further improve performance. The results achieved in this project contribute to the ongoing pursuit of power-efficient and high-performance processor designs based on the RISC-V architecture.

Truncated multiplication and batch software SIMD AVX512 implementation for faster Montgomery multiplications and modular exponentiation

This paper presents software implementations of batch computations, dealing with multi-precision integer operations. In this work, we use the Single Instruction Multiple Data (SIMD) AVX512 instruction set of the x86-64 processors, in particular the vectorized fused multiplier-adder VPMADD52. We focus on batch multiplications, squarings, modular multiplications, modular squarings and constant time modular exponentiations of 8 values using a word-slicing storage. We explore the use of Schoolbook and Karatsuba approaches with operands up to 4108 and 4154 bits respectively. We also introduce a truncated multiplication that speeds up the computation of the Montgomery modular reduction in the context of software implementation. Our Truncated Montgomery modular multiplication improvement offers speed gains of almost 20 % over the conventional non-truncated versions. Compared to the state-of-the-art GMP and OpenSSL libraries, our speedup modular operations are more than 4 times faster. Compared to OpenSSL BN_mod_exp_mont_consttimex2 using AVX512 and madd52* (madd52hi or madd52lo) in 256-bit registers, in fixed-window exponentiations of sizes 1024 and 2048 , our 512-bit implementation provides speedups of respectively 1.75 and 1.38, while the 256-bit version speedups are 1.51 and 1.05 for 1024 and 2048 -bit sizes (batch of 4 values in this case).

The Scale of Application of Electronic Documentary Communications as the Most Important Indicator for Assessing the Digitalization of Judicial Activities

The only way to speed up and ensure the quality of transmission and receipt of information between courts, participants in legal proceedings, bodies of the Judicial Department system and other entities is the use of modern information technologies. The system-structural, cultural, historical, sociological, statistical methods of scientific knowledge contributed to the implementation of the research objectives. The author defines the differences between the concepts of “documented information” and “documented communications”. The factors influencing the development of electronic documentary communications in the activities of courts have been established. Improving regulatory support is the leading of these factors. At the same time, interaction with the Federal Archival Agency in matters of creating legislation on office work in the Russian Federation was identified as a promising direction. Standardization and simplification of departmental normative regulation in modern conditions can be carried out by creating a single instruction for courts of general jurisdiction on judicial workflow, which should have a high degree of operational electronic component, taking into account the procedural features of the activities of various courts. Based on the proven experience of pilot courts and the use of available resources of the State Autonomous System “Pravosudie”, it seems appropriate to create a permanent system for monitoring the work of the apparatus of the courts in connection with the conduct of electronic documentary communications. The authorized federal subject, the Judicial Department, is entitled to administer this system. As a result of the study, the scientific basis for the practical implementation of the idea of replacing paper judicial documentary communications with electronic ones is determined – this is the cumulation of knowledge and methods of various knowledge systems – jurisprudence, information technology, document science and archival science.

Codebase release 1.1 for GAPS

The Single Instruction, Multiple Thread (SIMT) paradigm of GPU programming does not support the branching nature of a parton shower algorithm by definition. However, modern GPUs are designed to schedule threads with diverging processes independently, allowing them to handle such branches. With regular thread synchronisation and careful treatment of the individual steps, one can simulate a parton shower on a GPU. We present a Sudakov veto algorithm designed to simulate parton branching on multiple events in parallel. We also release a CUDA C++ program that generates matrix elements, showers partons and computes jet rates and event shapes for LEP at 91.2 GeV on a GPU. To benchmark its performance, we also provide a near-identical C++ program designed to simulate events serially on a CPU. While the consequences of branching are not absent, we demonstrate that a GPU can provide the throughput of a many-core CPU. As an example, we show that the time taken to shower 10^6106 events on one NVIDIA TESLA V100 GPU is equivalent to that of 295 Intel Xeon E5-2620 CPU cores.

An algorithm to parallelise parton showers on a GPU

The Single Instruction, Multiple Thread (SIMT) paradigm of GPU programming does not support the branching nature of a parton shower algorithm by definition. However, modern GPUs are designed to schedule threads with diverging processes independently, allowing them to handle such branches. With regular thread synchronisation and careful treatment of the individual steps, one can simulate a parton shower on a GPU. We present a Sudakov veto algorithm designed to simulate parton branching on multiple events in parallel. We also release a CUDA C++ program that generates matrix elements, showers partons and computes jet rates and event shapes for LEP at 91.2 GeV on a GPU. To benchmark its performance, we also provide a near-identical C++ program designed to simulate events serially on a CPU. While the consequences of branching are not absent, we demonstrate that a GPU can provide the throughput of a many-core CPU. As an example, we show that the time taken to shower 10^6106 events on one NVIDIA TESLA V100 GPU is equivalent to that of 295 Intel Xeon E5-2620 CPU cores.

Accelerating real-time deterministic discovery through single instruction multiple data graphical processor unit for executing distributed event logs

With the rapid expansion of process mining implementation in global enterprises distributed across numerous branches, there is a critical requirement to develop an application qualified for real-time operation with fast and precise data integration. To address this challenge, computational parallelism emerges as a feasible solution to accelerate data analytics, with graphical processor unit (GPU) computing currently trending for achieving parallelism acceleration. In this study, we developed a process mining application to optimize parallel and distributed process discovery through a combination of central processing unit (CPU) and GPU computing. The use of this computing combination is leveraged for executing multi-windowing threads within multi-instruction, multiple data (MIMD) in the CPU for streaming distributed event logs, using multi-instruction, single data (MISD) within the CPU to deploy a large footprint pipeline to the GPU, and then utilizing single instruction, multiple data (SIMD) to execute global thread discovery within the GPU. This method significantly accelerates performance in real-time distributed discovery. By reducing branch divergence in SIMD on the global thread GPU parallelism, it outperformed local-thread CPU execution in deterministic discovery, speeding up from 10 to 40 times under specific conditions using a novel min-max flag algorithm implemented within the main steps of the process discovery.

State of What Art? A Call for Multi-Prompt LLM Evaluation

Abstract Recent advances in LLMs have led to an abundance of evaluation benchmarks, which typically rely on a single instruction template per task. We create a large-scale collection of instruction paraphrases and comprehensively analyze the brittleness introduced by single-prompt evaluations across 6.5M instances, involving 20 different LLMs and 39 tasks from 3 benchmarks. We find that different instruction templates lead to very different performance, both absolute and relative. Instead, we propose a set of diverse metrics on multiple instruction paraphrases, specifically tailored for different use cases (e.g., LLM vs. downstream development), ensuring a more reliable and meaningful assessment of LLM capabilities. We show that our metrics provide new insights into the strengths and limitations of current LLMs.

Parallel Implementation of K-Best Quadrature Amplitude Modulation Detection for Massive Multiple Input Multiple Output Systems

Massive MIMO (Multiple Input Multiple Output) systems impose significant processing burdens along with strict latency requirements. The combination of large-scale antenna arrays and wide bandwidth requirements for next-generation wireless systems creates an exponential increase in frontend to backend data. Balancing the processing latency and reliability is critical for baseband processing tasks such as QAM detection. While linear detection algorithms have low computational complexity, their use in Massive MIMO scenario has heavy degradation in error performance. Nonlinear detection methods such as Maximum Likelihood and Sphere Decoding have good error performance, but they suffer from high, variable, and uncontrollable computational complexity. For such cases, the K-best QAM detection algorithm can provide required control over the system performance while maintaining near-ML error performance. In this paper, hard-output, as well as soft-output K-best QAM detection, is implemented in a CPU by utilizing the multiple cores combined with vector processing. Similarly, hard-output detection in a GPU is implemented by leveraging the SIMD (Single Instruction, Multiple Data) architecture and Warp-based execution model. The processing time per bit and the energy consumption per bit are compared for CPU and GPU implementations for QAM constellation density and MIMO array size. The GPU implementation shows up to 5× processing latency per bit improvement and up to 120× energy consumption per bit improvement over the CPU implementation for typical QAM constellations such as 4, 16, and 64 QAM. GPU implementation also shows up to 125× improvement over CPU implementation in energy consumption per bit for larger MIMO configurations such as 24 × 24 and 32 × 32. Finally, the soft-output detector is combined with a LDPC (Low-Density Parity Check) decoder to obtain the FER (Frame Error Rate) performance for CPU implementation. The FER is then combined with frame processing latency to form a Goodput metric to demonstrate the latency and reliability tradeoff.

Instruct Pix-to-3D: Instructional 3D object generation from a single image

We study a challenging task, creating the instructional 3D object based on a single image and human instruction. Although existing methods utilize pre-trained text-to-image diffusion models to optimize Neural Radiance Fields (NeRF) and achieve remarkable results, they are inherently challenged in addressing this task due to two inherent obstacles. First, the written instruction is mismatched or uncorrelated with target images in the distribution of pre-trained text-to-image diffusion models, which leads to insufficient supervision. Another is editing 3D content starting from a single image, which is an ill-posed problem as the image only provides partial information. To tackle the difficulties, we propose an Instruct Pixel-to-3D framework, which exploits the supervisory signals from the given instructions and integrates the domain-specific knowledge drawn from 2D and 3D diffusion models. Specifically, to address the first challenge, we propose instruction guidance to facilitate meticulous image editing using fine-grained instructions and regulate the novel views of 3D objects using positional prompts. To tackle the second difficulty, we propose diffusion guidance for 3D generation, which optimizes the NeRF employing dual guidances: a 2D diffusion guidance derived from the score distillation sampling (SDS) loss and a 3D diffusion guidance embodied by the Zero-1-to-3 loss. Moreover, Instruct Pix-to-3D adopts a coarse-to-fine training strategy aimed at mitigating the complexities inherent in reconstructing scenes from sparse viewpoints. Qualitative and quantitative experiments on the DTU dataset and in-the-wild images demonstrate that our approach could synthesize high-quality and high-fidelity 3D content based on a single image and human instruction.

Enhancing computational efficiency in 3-D seismic modelling with half-precision floating-point numbers based on the curvilinear grid finite-difference method

SUMMARY Large-scale and high-resolution seismic modelling are very significant to simulating seismic waves, evaluating earthquake hazards and advancing exploration seismology. However, achieving high-resolution seismic modelling requires substantial computing and storage resources, resulting in a considerable computational cost. To enhance computational efficiency and performance, recent heterogeneous computing platforms, such as Nvidia Graphics Processing Units (GPUs), natively support half-precision floating-point numbers (FP16). FP16 operations can provide faster calculation speed, lower storage requirements and greater performance enhancement over single-precision floating-point numbers (FP32), thus providing significant benefits for seismic modelling. Nevertheless, the inherent limitation of fewer 16-bit representations in FP16 may lead to severe numerical overflow, underflow and floating-point errors during computation. In this study, to ensure stable wave equation solutions and minimize the floating-point errors, we use a scaling strategy to adjust the computation of FP16 arithmetic operations. For optimal GPU floating-point performance, we implement a 2-way single instruction multiple data (SIMD) within the floating-point units (FPUs) of CUDA cores. Moreover, we implement an earthquake simulation solver for FP16 operations based on curvilinear grid finite-difference method (CGFDM) and perform several earthquake simulations. Comparing the results of wavefield data with the standard CGFDM using FP32, the errors introduced by FP16 are minimal, demonstrating excellent consistency with the FP32 results. Performance analysis indicates that FP16 seismic modelling exhibits a remarkable improvement in computational efficiency, achieving a speedup of approximately 1.75 and reducing memory usage by half compared to the FP32 version.

The effects of conscious movement investment on inhibiting a golf stroke

Previous studies have suggested an association between conscious movement investment and inhibiting motor actions. However, no within-designs were used in which conscious movement investment was manipulated. The current study compared changes in inhibition after instruction interventions that aimed to expand and limit conscious investment in the execution of a golf putting task. During a baseline and post-intervention test, participants were asked to putt balls in a hole. Randomly, an auditory stop-signal appeared 50 ms after reaching the end of backswing on some trials, signalling them to stop the downswing as quickly as possible. Between the two tests, the participants practiced under different instructions, without the stop-signal. One group (i.e., expanded conscious investment, ECIG) received multiple explicit movement-related instructions along with the internal focus of attention instructions, while the second group (i.e., limited conscious investment, LCIG) received a single analogy instruction paired with external focus of attention instructions. The results did not reveal significant differences in stopping rate and stopping time between the baseline and post-intervention tests and the two groups. However, a mediation analysis highlighted that the ECIG exhibited a greater change in downswing time compared to the LCIG. This change was correlated with a larger increase in stopping rate and stopping time. We conclude that conscious movement investment did not directly influence inhibition. Instead, we discuss how conscious movement investment may indirectly influence inhibition dependent on the putting kinematics.

Efficient and Portable Vectorized Sweep Kernels for the Transport Equation on 3D Cartesian Grids Using the Kokkos Framework

This paper describes the implementation of efficient and portable vectorized sweep kernels as part of the resolution of the neutron transport equation on three-dimensional Cartesian grids using the discrete ordinates ( S n ) method for the angular variable and the diamond differencing (DD) scheme for the spatial discretization. Vectorization is set up along the directions within the same octant and is independent of the spatial discretization order; therefore, the extension of this technique to high-order DD or discontinuous Galerkin schemes is immediate. Our implementation is written in C++17 and relies on the Kokkos performance portability framework. This library allows one to express shared-memory parallelism (including vectorization) in a machine-independent way and supports many backends including CUDA and OpenMP. Our vectorization procedure relies on the portable single instruction multiple data types provided by Kokkos. The method has been implemented for DD schemes up to order 2 and yields promising results on CPUs supporting standard vector instructions.

Universe is Ether based Single Instruction Quantum Computer his Activity Creates Matter and Life

Universe is actually gigant quantum computer (Seth Lloyd) made of ether – multi coloured, multilayered super conductor (Frank Wilczek). Ether constantly creates elementary particles (electron and proton), which are subjet of universe quantum computer macro instruction – Charge Neutralization Process –CNP. After matter creation (periodic table of elements), single cell organisms and life itself (rna and dna) emerged.

Implementation and Evaluation of SIMD Instructions using RISC-V

This thesis introduces and explores the design and verification of a packed Single Instruction, Multiple Data (SIMD) instruction set for a RISC-V processor, known as the RISC-V P extension. This extension enhances the RISC-V instruction set architecture by providing packed SIMD support for 8-bit, 16-bit, and 32-bit integer data types. The significance of this architecture lies in its potential to empower developers in constructing more efficient and powerful data-parallel programs for RISC-V processors. This contribution enhances the overall capabilities of the RISC-V ecosystem, providing a valuable extension to the instruction set architecture for data-parallel applications. Keywords: Data-parallel Programs, instruction set architecture, RISC-V, P extension, Packed SIMD

The updates in Libcint 6: More integrals, API refinements, and SIMD optimization techniques.

Libcint is a library designed for the evaluation of analytical integrals for Gaussian type orbitals. It prioritizes simplicity, ease of use, and efficiency for the development of quantum chemistry programs. In the release of version 6.0, Libcint supports the computation of integrals for various operators, such as overlap, Coulomb, Gaunt, Breit, attenuated Coulomb, Slater-type geminals, and Yukawa potential, as well as arbitrary orders of derivatives for these operators. To enhance the usability of the library, Libcint provides a uniform function signature for all integral functions. A code generator is included to automate the implementation of new integrals. To achieve better performance on modern central processing unit architectures, the library employs explicit single instruction multiple data parallelization in the code implementation.

Harnessing Manycore Processors with Distributed Memory for Accelerated Training of Sparse and Recurrent Models

Current AI training infrastructure is dominated by single instruction multiple data (SIMD) and systolic array architectures, such as Graphics Processing Units (GPUs) and Tensor Processing Units (TPUs), that excel at accelerating parallel workloads and dense vector matrix multiplications. Potentially more efficient neural network models utilizing sparsity and recurrence cannot leverage the full power of SIMD processor and are thus at a severe disadvantage compared to today's prominent parallel architectures like Transformers and CNNs, thereby hindering the path towards more sustainable AI. To overcome this limitation, we explore sparse and recurrent model training on a massively parallel multiple instruction multiple data (MIMD) architecture with distributed local memory. We implement a training routine based on backpropagation though time (BPTT) for the brain-inspired class of Spiking Neural Networks (SNNs) that feature binary sparse activations. We observe a massive advantage in using sparse activation tensors with a MIMD processor, the Intelligence Processing Unit (IPU) compared to GPUs. On training workloads, our results demonstrate 5-10x throughput gains compared to A100 GPUs and up to 38x gains for higher levels of activation sparsity, without a significant slowdown in training convergence or reduction in final model performance. Furthermore, our results show highly promising trends for both single and multi IPU configurations as we scale up to larger model sizes. Our work paves the way towards more efficient, non-standard models via AI training hardware beyond GPUs, and competitive large scale SNN models.