Single-grain Thin-film Transistors Research Articles

Formation of regularly arranged large grain silicon islands by using embedded micro mirrors in the flash crystallization of amorphous silicon

The well-controlled formation of large silicon grains on predetermined positions is a key issue in order to produce single-grain thin film transistors on insulating substrates and thus to enable monolithic 3D integration. One way to achieve this is to artificially control the solidification of molten silicon during the flash crystallization of amorphous silicon. In this work, we present such an approach in which we used patterned metal layers below the amorphous silicon. The metal spots act as embedded micro mirrors and consequently introduce a lateral temperature gradient into the silicon film during flash crystallization. As a result, the grain growth from molten silicon is seeded from the predefined regions with the lowest temperature and thus the formation of large crystal silicon islands proceeds in a controlled manner. In the scope of this study, we evaluated a variety of different mirror patterns with respect to their suitability for this approach and observed that patterns of both circular and line-shaped mirrors are the most promising variants. The resulting silicon islands have pillow-like shapes and are located exclusively in regions between neighboring mirrors. They exhibit dimensions of a few tens of micrometers and consist of grains with sizes up to 28 μm. The formation of single-grain silicon pillow-like structures was observed for particular mirror patterns having circular mirrors. On the other hand, the application of mirror patterns with line-shaped mirrors resulted in the formation of elongated silicon grains which we explained in terms of lateral solidification starting from one edge. Furthermore, this approach exhibits grain filter characteristics leading to the controlled growth of large single grains at predetermined positions.

Flexible Smart Display with Integrated Graphics Rasterizor using Single Grain TFTs

Flexible electronics is a fast emerging market and includes electronics fabricated on flexible substrates, large area displays, low cost and disposable electronics. Both research and commercial institutions around the world have been trying to develop low temperature processes which will enable fabrication of electronic devices on arbitrary substrates including glass and plastic. While most of these technologies are still in the research phase, many approaches have shown promising results. One such technology is being developed in DIMES, TU Delft which uses single grain silicon crystals to fabricate Single Grain Thin Film Transistors (SG-TFTs) at plastic compatible temperatures. SG-TFTs and other similar technologies can potentially enable fabricating electronics directly on arbitrary substrates. This would further enable integration of embedded intelligence in devices that would enhance the current functionalists of displays. This paper is an effort in this direction as it undertakes a study to design a flexible display with an integrated graphics rasterizor unit. The paper introduces the novel idea to move parts of the graphics pipeline from the CPU/GPU to the display. This will add intelligence to the display so as to realize a smart-display. The paper proposes several architectures for implementing a rasterizor unit on smart-display, conceptually fabricated on a flexible substrate using SG-TFT technology. While the transistors fabricated with SG-TFT and similar technologies are relatively slower than the standard CMOS, this paper proposes and concludes that a tile based system design can potentially result into enhanced system performance.

Towards the Integration of Carbon Nanotubes as Vias in Monolithic Three-Dimensional Integrated Circuits

Carbon nanotubes (CNT) can be an attractive candidate for vertical interconnects (vias) in three-dimensional integrated circuits due to their excellent thermal and electrical properties. To investigate the electrical resistivity of CNT, test vias were fabricated using both a top-down and bottom-up approach. The measured resistivity for the top-down process of 10 mΩ cm is among the better values found in literature. Beside this, the ability to grow CNT directly on single-grain thin-film transistors (SG-TFT) was demonstrated. The electrical performance of the SG-TFT was found not to be influenced by the CNT growth.

Hot Carrier Effect and Tunneling Effect of Location- and Orientation-Controlled (100)- and (110)-Oriented Single-Grain Si TFTs Without Seed Substrate

We report on high-performance (100)and (110)-oriented single-grain thin-film transistors (SG-TFTs) below 600°C obtained through the orientation-controlled μ-Czochralski process. Surface and in-plane orientation control allows uniformity to approach that of the silicon-on-insulator counterpart. Electron mobilities are 732 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /Vs for (100) and 630 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /Vs for (110). Devices exhibit stable performance under both gate and drain stress. After applying electrical stress on the gate and the drain for 1000 s, no deterioration in electron mobility was observed for either (100) SG-TFT or (110) SG-TFT. A kink effect was observed in the output characteristic at a high drain voltage. The higher voltage of drain stress enhances impact ionization, which induces an increase in the kink current. At a higher drain bias, interface trap states at the drain side were created, which, in turn, decrease the kink current. "Asymmetric" output characteristics were also observed after the drain bias. The asymmetric performance confirms that the interface traps are generated at the drain side. Under a negative gate bias, electrons tunneling through the drain to the channel dominate the deterioration of the device with a positive shift of the V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> SG-TFT showing more stable performance than poly-Si TFT under different stress conditions.

Location- and Orientation-Controlled (100) and (110) Single-Grain Si TFTs Without Seed Substrate

This paper reports on high-performance (100)- and (110)-oriented single-grain thin-film transistors (SG-TFTs) fabricated below 600°C without any seed substrate. Orientation has been controlled by μ-Czochralski process with an excimer laser. The field-effect mobility of the n-channel transistor is 998 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /V·s for (100) SG-TFTs and 811 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /V·s for (110) SG-TFTs. The field-effect mobility of the p-channel transistor is 292 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /V ·s for (100) SG-TFTs and 429 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /V ·s for (110) SG-TFTs.

High Speed Six-Transistor Static Random Access Memory Cells Using Single Grain Thin Film Transistors Fabricated at Low Temperature Process

In this paper we will report successfully fabricated six transistor static random access memory (6T SRAM) cells using single-grain thin film transistors (TFTs). SRAM cells have been designed by analytical calculations and verified by DC and transient simulations. TFTs are fabricated by µ-Czochralski process that consists of making grain filter and Excimer laser crystallization at temperatures below 550 °C. The gate length of transistors are 2 µm. Fabricated SRAM cells based on single grain TFTs, show good read and write static noise margin (SNM and WNM) equal to 0.55 and 0.75 V at 3.3 V power supply, respectively. Finally, excellent read and write access times equal to 13 and 8 ns in 87 MHz worldline frequency were obtained.

Stacking of Single-Grain Thin-Film Transistors

Vertical stacking of transistors is a promising technology which can realize compact and high-speed integrated circuits (ICs) with a short interconnect delay and increased functionality. Two layers of low-temperature fabricated single-grain thin-film transistors (SG TFTs) have been monolithically integrated. Using a finite element method (FEM) simulation, the damage to the bottom layer devices during laser crystallization of the top layer silicon layer has been investigated. N-channel metal–oxide–semiconductor (n-MOS) mobilities are 565 and 393 cm2 V-1 s-1 and p-channel MOS (p-MOS) mobilities are 159 and 141 cm2 V-1 s-1, for the top and bottom layers respectively. A three-dimensional (3D) complementary MOS (CMOS) inverter has also been fabricated, with one transistor on the bottom layer and the other on the top layer.

Reliability Analysis of Single Grain Si TFT using 2D Simulation

Single grain thin-film transistors (SG-TFTs) fabricated inside a location-controlled grain by µ-Czochralski process have as high as SOI performance despite low-temperature process. Reliability of SG-TFTs is a very important issue. The degradation effects of SG-TFTs under bias-stress conditions are mostly mobility degradation, threshold voltage changing, subthreshold characteristic degradation. These effects need to be modeled in order to predict the reliability for any bias-stress conditions applied to the device. To obtain that, extraction parameters strategy of degradation model has to be found out. The degradation model is thus confirmed for different bias-stress conditions.

Single-grain Si thin-film transistors SPICE model, analog and RF circuit applications

Single-grain thin-film transistors (SG-TFTs) fabricated inside location-controlled using μ-Czochralski process exhibit SOI-FETs like performance despite processing temperatures remaining below 350°C. Thus, the SG-TFT is a potential technology for large-area highly-integrated electronic system and system-in-package, taking advantage of the system-on-flexible substrate and low manufacturing cost capabalities. The SG-TFT is modeled based on the BSIMSOI SPICE model where the mobility parameter is modified to fit the SG-TFT behavior. Therefore, analog and RF circuits can be designed and benchmarked. A two-stage telescopic cascode operational amplifier fabricated in a prototype 1.5μm SG-TFT technology demonstrates DC gain of 55dB and unity-gain bandwidth of 6.3MHz. A prototype CMOS voltage reference demonstrates a power supply rejection ratio (PSRR) of 50dB. With unity-gain frequency, fT, in the GHz range, the SG-TFT can also enable RF circuits for wireless applications. A 12dB gain RF cascode amplifier with integrated on-chip inductors operating in the 433MHz ISM band is demonstrated.

Monolithic 3D Integration of Single-Grain Si TFTs

ABSTRACTVertical stacking of transistors is a promising technology which can realize compact and high-speed integrated circuits (ICs) with a short interconnect delay and increased functionality. Two layers of low-temperature fabricated single-grain thin-film transistors (SG TFTs) have been monolithically integrated. NMOS mobilities are 565 and 393 cm2/Vs and pMOS mobilities are 159 and 141 cm2/Vs, for the top and bottom layers respectively. A three-dimensional (3D) inverter has also been fabricated, with one transistor on the bottom layer and the other on the top layer. The inverters showed an output voltage swing of 0 to 5 V with a switching voltage of around 2 V.

SPICE Modeling of Single-Grain Si TFTs using BSIMSOI

Single Grain Thin-film transistors (SG-TFTs) fabricated inside a location-controlled grain by µ-Czochralski process have as high as SOI performance. To model them, BSIMSOI with a proper modification of the mobility is proposed. The model has been verified for n- and p-channel DC and low frequency AC conditions by comparison with measurement results. Furthermore, preliminary circuit simulations are executed.

Influence of trap states on dynamic properties of single grain silicon thin film transistors

The transient properties of single grain–thin film transistors (SG-TFTs) with high electron mobility have been studied. Overshoot current induced by trap states has been observed in most of the devices. A method of ac measurements has been used to investigate the trap processes. Both transient and ac measurements show that the response of some SG-TFTs with high field effect mobility is dominated by a single trap level. Bias stressing on SG-TFT can induce more trap states and thus change the ac response of the device.

Preparation of Large, Location-Controlled SI Grains by Excimer Laser Crystallization of α-SI FILM SPUTTERED AT 100°C

AbstractLocation-controlled grains with a diameter of 4 μm are successfully prepared by excimer laser crystallization of sputtered α-Si with μ-Czochralski (grain filter) process at a maximum processing temperature of 100°C. By a pulsed DC magnetron sputtering, α-Si film is deposited firstly on non-structured oxidized wafers for a test. It is found that a-Si film is easily ablated even with a low laser fluence when it is deposited with a substrate bias. From a non-biased sputtered α-Si precursor, grains with 1.8 mm in diameter can be prepared with excimer laser crystallization at room temperature. α-Si is then sputtered on the SiO2 with narrow holes (grain filters) and crystallized at room temperature. The location-controlled grains can be successfully prepared in a large energy density window. These location-controlled grains with a low temperature process are promising for single-grain thin film transistors (TFTs) on plastic substrate for an application to system integration on flexible microelectronics.

Defect States in Excimer-Laser Crystallized Single-Grain TFTs Studied with Isothermal Charge Deep-level Transient Spectroscopy

AbstractDefect states were quantitatively evaluated in single-grain (SG) Si thin-film transistors (TFTs), prepared by micro-Czochralski (grain filter) process with excimer-laser crystallization, by means of isothermal charge deep-level transient spectroscopy with a high sensitive charge/voltage converter. Its sensitivity reaches 10-16 C and it operates in the range of 2 microseconds - 10 ms. Measurements were performed on the SG-Si TFTs with various energy densities of laser crystallization, various channel areas, and positions in the grain. Our results indicate a direct correlation of fabrication parameters, parameters of the TFT determined from its transfer characteristics, and parameters of defect states (energy position in the band gap, concentration) induced by coincidence site lattice boundaries inside the location-controlled grains and by defects in the grain filter.