Hot Carrier Effect and Tunneling Effect of Location- and Orientation-Controlled (100)- and (110)-Oriented Single-Grain Si TFTs Without Seed Substrate

Abstract

We report on high-performance (100)and (110)-oriented single-grain thin-film transistors (SG-TFTs) below 600°C obtained through the orientation-controlled μ-Czochralski process. Surface and in-plane orientation control allows uniformity to approach that of the silicon-on-insulator counterpart. Electron mobilities are 732 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /Vs for (100) and 630 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /Vs for (110). Devices exhibit stable performance under both gate and drain stress. After applying electrical stress on the gate and the drain for 1000 s, no deterioration in electron mobility was observed for either (100) SG-TFT or (110) SG-TFT. A kink effect was observed in the output characteristic at a high drain voltage. The higher voltage of drain stress enhances impact ionization, which induces an increase in the kink current. At a higher drain bias, interface trap states at the drain side were created, which, in turn, decrease the kink current. "Asymmetric" output characteristics were also observed after the drain bias. The asymmetric performance confirms that the interface traps are generated at the drain side. Under a negative gate bias, electrons tunneling through the drain to the channel dominate the deterioration of the device with a positive shift of the V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> SG-TFT showing more stable performance than poly-Si TFT under different stress conditions.