Stacking of Single-Grain Thin-Film Transistors

Abstract

Vertical stacking of transistors is a promising technology which can realize compact and high-speed integrated circuits (ICs) with a short interconnect delay and increased functionality. Two layers of low-temperature fabricated single-grain thin-film transistors (SG TFTs) have been monolithically integrated. Using a finite element method (FEM) simulation, the damage to the bottom layer devices during laser crystallization of the top layer silicon layer has been investigated. N-channel metal–oxide–semiconductor (n-MOS) mobilities are 565 and 393 cm2 V-1 s-1 and p-channel MOS (p-MOS) mobilities are 159 and 141 cm2 V-1 s-1, for the top and bottom layers respectively. A three-dimensional (3D) complementary MOS (CMOS) inverter has also been fabricated, with one transistor on the bottom layer and the other on the top layer.