Single Flux Quantum Circuits Research Articles

A Local Optimization Method for Single Flux Quantum Logic Circuits Design Utilizing Synchronizer IPs

In the post-Moore era, slow-growing operating frequency and massive power dissipation make researchers seek new developing directions in integration circuits (ICs). The single flux quantum (SFQ) circuit, a type of superconducting digital circuit, is regarded as an alternative circuit for future computing technology. SFQ circuits are natural gate-level-pipelining synchronous sequential circuits requiring path balancing. However, path balancing may consume enormous resources, as the logic levels of fan-in gates of most gates are different, with the consumption originating from the extra gates (D-Flip-Flops, DFFs) for path balancing and the routing with a much larger clock tree. Hence, in this article, we propose a local optimization method to address the vast consumption problem of the clock tree caused by path balancing in SFQ circuits, primarily relying on self-developed electronic design automation tools for the JSICcomplier for SFQ circuits and using the SIMIT Nb03 cell library. Moreover, we design synchronizer IPs called Dsyn series to replace DFFs in path balancing. The clock nodes and the clocking path consumption are highly reduced by utilizing the proposed strategy, while the new series can be recognized as IPs and easily added to our library, affording scalability. Experiments in a demo S-box circuit demonstrated a percentage of Josephson junctions reduction in clock tree up to 36.48%, while on a few benchmark circuits, the corresponding results are up to 50.69%, demonstrating our method's effectiveness.

VHDL models of the basic dual-rail asynchronous RSFQ gates

This paper presents a basic approach for applying Very High-Speed Integrated Circuits Hardware Description Language (VHDL) descriptions of dual-rail rapid single flux quantum circuits (RSFQ). Because RSFQ is naturally pulsed, dual-rail data encoding encourages event driven data processing at very high speeds. A method for suitable simulation models of the basic asynchronous RSFQ gates is described. The realization of VHDL models is performed in relation with the subsequent implementation for simulation and parameter optimization of complex logic cells.

A Hybrid Josephson Transmission Line and Passive Transmission Line Routing Framework for Single Flux Quantum Logic

The single flux quantum (SFQ) logic family is a novel digital logic as it provides ultrafast and energy-efficient circuits. For large-scale SFQ circuit design, specialized electronic design automation (EDA) tools are required due to the differences in logic type, timing constraints, and circuit architecture, in contrast to the Complementary metal–oxide–semiconductor (CMOS) logic. In order to improve the overall performance of an SFQ circuit, an efficient routing algorithm should be applied during the layout design to perform accurate timing adjustment for fixing hold violations and optimizing critical paths. Thus, a hybrid Josephson transmission line and passive transmission line routing framework is proposed. It consists of four main modules and an exploration of the potential timing performance based on the given layout placement. The proposed routing tool is demonstrated on seven testbench circuits. The obtained results demonstrate that the operating frequency is greatly improved, and all the hold violations are eliminated for each circuit.

Serial Biasing Technique for Electronic Design Automation in RSFQ Circuits

There has been renewed interest and efforts in increasing the complexity of superconductor circuits by means of electronic design automation (EDA). Serial biasing (SB) is a technique that reduces the total dc bias current required by large rapid single flux quantum (RSFQ) circuits, including its energy-efficient variant, ERSFQ. We believe SB needs to be incorporated in any EDA flow for large circuits. In SB, equally biased circuit blocks are placed on galvanically isolated islands and biased in series. SFQ pulses are transferred between islands by means of driver-receiver pairs (DRPs). The special current management technique, called the grapevine (GV) approach and introduced earlier, is used to handle the bias current flowing in and out of an island. In this article, we present all required layout primitives needed to implement SB for the IARPA-led SuperTools cell library that targets the SFQ5ee fab node at MIT Lincoln Laboratory. We discuss the horizontal and vertical composite driver-receiver pairs that comprise not only DRPs but also transmitters and receivers for passive transmission lines. We present the basic blocks to implement the GV managing technique for current injection and extraction. As a proof of concept, we designed a four-island test circuit that comprises all discussed layout primitives and employs an on-chip pseudorandom binary sequence generator as a test pattern source. The test circuit worked up to 50 GHz at the BER level of 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">−12</sup> . We discuss future steps to improve the SB technique.

Optimization of Suzuki Stack Circuit to Reduce Power Dissipation

Superconductor–semiconductor hybrid circuits can combine the benefits of the high-speed and low-power operation of single-flux quantum circuits and high integration densities of CMOS technology such as memory. The Suzuki stack, a type of Josephson latching driver/amplifier, is a widely used interface circuit in Josephson–CMOS hybrid memories. Due to the limited cooling power at cryogenic temperatures, the power dissipation is becoming an important concern, especially in large-scale systems. An optimization technique to significantly reduce the power dissipation of Suzuki stack circuits is proposed in this article. The proposed design can reduce the power dissipation by 30–70% while causing a voltage drop of 2–9% in the output voltage depending on the circuit parameter configuration. The tradeoffs between the power dissipation and output voltage characteristics are discussed. The proposed design can operate correctly within at least <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\pm$</tex-math></inline-formula> 20% of process parameter variations as demonstrated with extensive simulations.

On-chip test vector generation and downsampling for testing RSFQ circuits

An on-chip high-frequency testing method for rapid single flux quantum circuits is proposed. This method employs test vectors based on pseudo-random sequences created by an on-chip high-frequency clock generator (CG) and a linear feedback shift register with parallel outputs (LSPO). Downsamplers (DSMs) at the outputs of a circuit under test (CUT) decimate the CUT output data so that high-frequency testing can be performed at sufficiently low data rates between the CUT and room-temperature electronics. The proposed testing can continuously test the circuit at high frequency with low-cost instruments. All of the critical subsystems, including LSPO, CG, and DSM, were designed, fabricated, and successfully tested. We validated proper operation at up to 40 GHz, confirming the concept and execution.

Extended FDTD Method for Coanalysis of Superconducting Passive Transmission Lines and Josephson Junction Drivers and Receivers

In rapid single-flux quantum circuits, the signal integrity problem of superconducting passive transmission lines (PTLs) becomes critical. In this article, an extended 3-D finite-difference time-domain (FDTD) method is proposed for coanalysis of superconducting PTLs and Josephson junction (JJ) drivers and receivers. The central difference FDTD scheme is used for PTLs, and the backward difference method is adopted for JJs, which are introduced to FDTD cells as lumped elements. Due to the nonlinearity of JJs, the Newton–Raphson method is introduced to solve the boundary condition of the FDTD method. Compared with the 1-D FDTD method of the transmission line model of PTLs, the proposed method performs full-wave analysis of the physical structure of PTLs. Therefore, the proposed 3-D FDTD method is theoretically more accurate than the conventional method by avoiding parameter extraction and circuit analysis.

A Novel Clock Tree Aware Placement Methodology for Single Flux Quantum Logic Circuits With Maximum Path Length Consideration

In a single-flux-quantum (SFQ) circuit, almost all cells need to receive the clock signal that incurs a high clock routing overhead. Besides, the clock tree of an SFQ circuit requires the insertion of a clock splitter cell at every tree branching point that renders the conventional design flow of placement followed by clock tree synthesis (CTS) ineffective to obtain a high quality clock tree with low clock skew. Moreover, very few works in the literature attempted to minimize the maximum path length during SFQ circuit placement. The maximum path length, which is the length of the longest source-to-sink path of any data signal, should be minimized to achieve a higher final performance and to reduce the overhead for length matching in subsequent routing. To address these issues, we propose a two-stage global placement methodology and a placement refinement algorithm after placement legalization. Our two-stage global placement methodology first applies a conventional global placement algorithm to place the cells in the given SFQ circuit evenly, which is followed by CTS and clock splitter insertion, and then, performs a second stage of global placement to replace both the original cells and clock splitters at the same time. In the second global placement stage, the look-ahead legalization technique is used to spread out the original cells and the clock splitters, and the clock tree is resynthesized several times to obtain an optimized clock tree topology such that there are little overlaps of the clock splitters with the original circuit cells. We propose a novel net model in global placement that facilitates the concurrent optimization of the total wirelength and the maximum path length. After legalizing the placement of all cells, a specialized placement refinement method is run to further reduce the clock skew and the maximum path length. Compared with the previous state-of-the-art work, on average, we reduced the total half-perimeter wirelength by 9%, reduced the maximum path length by 58%, and reduced the clock skew by 32%.

Flux Mitigation in Wide Superconductive Striplines

The increasing complexity of modern superconductive circuits, and single flux quantum (SFQ) circuits in particular has made the issue of flux trapping of growing importance. The use of wide superconductive striplines for signal routing has exacerbated this issue. Trapping residual magnetic fields in these striplines degrades performance while reducing margins, damaging the operability of superconductive circuits. In this article, an area efficient topology for striplines is introduced to manage flux trapping in large scale SFQ circuits. This topology is composed of narrow parallel lines in series with small resistors. The proposed topology decreases the length of the striplines by exploiting the mutual inductance between the narrow parallel lines. The topology requires significantly less area while preventing flux trapping within wide superconductive striplines. The narrow parallel line topology also reduces coupling capacitance between striplines. The proposed approach is compatible with automated routing of large scale SFQ integrated circuits.

Compact Stochastic Computing Circuits Using the Latching Function of RSFQ Circuits for Computing Polynomials

Stochastic computing (SC) is a method of expressing a numerical value by the appearance ratio of 1 in a bitstream to perform an operation. Rapid single flux quantum (RSFQ) circuits can handle SC naturally and operate at ultra-high speed. RSFQ SC circuits are suitable for applications tolerating error. This paper presents a design method of RSFQ SC circuits to calculate polynomials. Using the proposed design method, an internal circuit is designed to feed bitstreams of coefficients from bitstreams of constant to reduce large stochastic number generators. The method inserts storage elements to reduce correlations of signals, and thereby reduce the calculation error of the circuit. Additionally, it minimizes the number of inserted D flip-flops utilizing the latching function of gate inputs of RSFQ logic gates.

Braiding Operations for a Topological Josephson Junction Array using SFQ Current Pulses

Majorana bound states (MBSs) can occur in topological Josephson junction (JJ) arrays with the presence of a fractional vortex with 2π-phase winding. It has been theoretically shown that the braiding operation can be achieved by using current pulses, compatible with single flux quantum (SFQ) technology. Therefore, we designed an SFQ logic circuit for the braiding operations of the topological JJ array using single flux quanta in a conventional JJ array. Braiding operations could be realized by an SFQ logic circuit with double flux quantum driver. To obtain positive and negative current pulses using the SFQ logic circuit, we used SFQ logic circuits with ac biasing for simulation. Finally, we confirmed the CNOT operation using an array-type SFQ circuit by means of simulation and estimated the CNOT operation speed.

A new LFSR based high-frequency test method for RSFQ circuit

Rapid single flux quantum (RSFQ) circuits have the advantages of high speed and low power consumption. The typical frequency of the RSFQ circuits is tens of GHz. Therefore, it is necessary to reliably test the high-frequency performance of RSFQ circuits simply and effectively. This paper proposes a new on-chip high-frequency testing method, which uses pseudo-random sequences generated by linear feedback shift register (LFSR) as the test vectors, and the output shift registers (SRs) to store the last piece of high-frequency testing result and read out it at low-frequency. Unlike the traditional high-frequency demonstration method of using the Input/Output SRs, our testing system can automatically generate a large number of test vectors to test the circuit at high frequency at low cost, making the whole high-frequency demonstration more reliable and convincing. On the other hand, this method is also a feasible and straightforward on-chip high-frequency test method for various RSFQ circuits. This work verified the proposed method, and the highest test frequency can reach 54 GHz while the circuit shows good operating margins.

Implementation of an 8-bit bit-slice AES S-box with rapid single flux quantum circuits

Rapid single flux quantum (RSFQ) circuits are a kind of superconducting digital circuits, having properties of a natural gate-level pipelining synchronous sequential circuit, which demonstrates high energy efficiency and high throughput advantage. We find that the high-throughput and high-speed performance of RSFQ circuits can take the advantage of a hardware implementation of the encryption algorithm, whereas these are rarely applied to this field. Among the available encryption algorithms, the advanced encryption standard (AES) algorithm is an advanced encryption standard algorithm. It is currently the most widely used symmetric cryptography algorithm. In this work, we aim to demonstrate the SubByte operation of an AES-128 algorithm using RSFQ circuits based on the SIMIT Nb03 process. We design an AES S-box circuit in the RSFQ logic, and compare its operational frequency, power dissipation, and throughput with those of the CMOS-based circuit post-simulated in the same structure. The complete RSFQ S-box circuit costs a total of 42237 Josephson junctions with nearly 130 Gbps throughput under the maximum simulated frequency of 16.28 GHz. Our analysis shows that the frequency and throughput of the RSFQ-based S-box are about four times higher than those of the CMOS-based S-box. Further, we design and fabricate a few typical modules of the S-box. Subsequent measurements demonstrate the correct functioning of the modules in both low and high frequencies up to 28.8 GHz.

Thermal Modeling of Rapid Single Flux Quantum Circuit Structures

The operation of rapid single flux quantum (RSFQ) circuits depends upon the superconductive properties of the Josephson junctions (JJs) and metal layers, which are highly dependent on the temperature. Increasing densities and frequencies of JJs in RSFQ circuits have created a need to accurately model the local ambient thermal environment. In this article, an analytic thermal model of RSFQ circuit structures targeting the MIT Lincoln Laboratory SFQ5ee 10 kA/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> technology is presented. The model is based on a network of thermal resistances, representing the heat generation and thermal paths within an RSFQ circuit. An error of less than 0.22% between the model and a numerical solver is achieved. To reduce the computational complexity, the sparsity of the matrix of thermal resistances among the nodes is increased by exploiting the effective radius of the heat spreading behavior. Ignoring the thermal effects of the heating elements outside of a target radius reduces the number of thermal resistances by 50%, increasing the maximum error of the model to only 0.26%.

Emerging Attacks on Logic Locking in SFQ Circuits and Related Countermeasures

Hardware security in single flux quantum (SFQ) circuits is an emerging research area due the increasing demand of data centers operating with sensitive information and the limited number of fabrication facilities, where certain stages can be compromised. An existing logic locking technique in SFQ circuits, that is based on supplying additional current with mutual inductance to change the circuit operation, is analyzed in this article. Two new attacks on this logic locking technique are proposed. In the first attack, the locked OR cell is reset by applying a specific input combination. As a result, the overall range of correct key values can be increased by approximately 18.8 and 32.9% depending on the location of the generated mutual inductance. In the second attack, an overproduction threat model is proposed, which significantly decreases the number of measurements needed to reveal the secret key from exponential to linear scale. As a case study, a 4-to-2 priority encoder optimized for SFQ applications is designed and logic locked. The proposed attack is performed on this locked design. Finally, potential countermeasures for each attack type are discussed with the corresponding tradeoffs.

A Logic Verification Framework for SFQ and AQFP Superconducting Circuits

Traditional logical equivalence checking (LEC), which plays a major role in the entire chip design process, faces challenges of meeting the requirements demanded by the many emerging technologies that are based on logic models different from the standard complementary metal oxide semiconductor (CMOS). In this article, we propose an LEC framework to be employed in the verification process of superconducting electronics (SCE). Our LEC framework is compatible with the existing CMOS technologies and can also check features and capabilities that are unique to SCE. For instance, the performance of nonresistively biased single-flux quantum (SFQ) circuits benefits from ultradeep pipelining, and verification of such circuits requires new models and algorithms. We, therefore, present the multicycle input dependency circuit model which is a novel model representation of design to explicitly capture the dependency of primary outputs of the circuit on sequences of internal signals and inputs. Embedding the proposed circuit model and several structural checking modules, the process of verification can be independent of the underlying technology and signaling. We benchmark the proposed framework on postsynthesis SFQ and 4-phase adiabatic quantum flux parametron netlists. Results show a comparative verification time of SFQ circuit benchmark, including 16-bit integer divider and ISCAS’85 circuits with respect to the ABC tool for similar CMOS circuits.

Photon number resolvability of multi-pixel superconducting nanowire single photon detectors using a single flux quantum circuit

Superconducting nanowire single-photon detectors (SNSPDs) are typical switching devices capable of detecting single photons with almost 100% detection efficiency. However, they cannot determine the exact number of incident photons during a detection event. Multi-pixel SNSPDs employing multiple read-out channels can provide photon number resolvability (PNR), but they require increased cooling power and costly multi-channel electronic systems. In this work, a single-flux quantum (SFQ) circuit is employed, and PNR based on multi-pixel SNSPDs is successfully demonstrated. A multi-input magnetically coupled DC/SFQ converter (MMD2Q) circuit with a mutual inductance M is used to combine and record signals from a multi-pixel SNSPD device. The designed circuit is capable of discriminating the amplitude of the combined signals in accuracy of Φ 0/M with Φ 0 being a single magnetic flux quantum. By employing the MMD2Q circuit, the discrimination of up to 40 photons can be simulated. A 4-parallel-input MMD2Q circuit is fabricated, and a PNR of 3 is successfully demonstrated for an SNSPD array with one channel reserved for the functional verification. The results confirm that an MMD2Q circuit is an effective tool for implementing PNR with multi-pixel SNSPDs.

Frequency synchronization of single flux quantum oscillators

We demonstrate the frequency synchronization of multiple single-flux quantum (SFQ) oscillators with different oscillation frequencies. To synchronize these SFQ oscillators, a common constant bias current is supplied to the SFQ oscillators without any bias resistors. When an SFQ oscillator oscillates at a frequency of f, the average voltage across the Josephson junction comprising the SFQ oscillator is , where is the flux quantum in the superconductor. The bias currents supplied to the SFQ oscillators are redistributed to eliminate the average voltage difference output from the SFQ oscillators. As a result, the oscillation frequencies of all the SFQ oscillators are synchronized. Simulation results indicate that SFQ oscillators with an oscillation frequency difference of more than 50 GHz can be synchronized. We experimentally demonstrate the frequency synchronization of two SFQ oscillators composed of circular Josephson transmission lines. Frequency synchronization is expected to contribute toward the development of a low-power stable clock source stabilizing SFQ circuit operation.

An 8-b Multiplier Using Single-Stage Full Adder Cell in Single-Flux-Quantum Circuit Technology

Single-flux-quantum (SFQ) circuits operate at higher frequencies with much lower power consumption when compared to their CMOS counterparts. Synchronous SFQ circuits require full path balancing by inserting D-Flipflops as needed, an operation that tends to greatly increase the number of gates in a circuit. To control this increase in the total number of gates, complex multi-input SFQ logic gates can be built and used to synthesize the circuits. In this work, a 1-b full adder is built with sum and carries as two individual single-stage SFQ gates. Both of the sum and the carry cells are demonstrated with their schematics and layouts. Postlayout simulation based on the extracted circuit parameters by InductEx is done by using JSIM and demonstrates the correct functionality of the proposed full adder design. Later, an 8-b signed multiplier using this newly designed single-stage full adder is implemented to illustrate the advantages of the new design. The structure and timing strategy of the multiplier as well as the simulation result are shown. In the end, circuits of different sizes are synthesized with the single-stage full adder circuit, and the results are discussed.

A cryogenic memory array based on superconducting memristors

A scalable cryogenic memory system is one of the prime requirements for the implementation of practical quantum computers, large-scale single flux quantum circuits, and space electronics. Here, we leverage the memristive behavior of a conductance-asymmetric superconducting quantum interference device (CA SQUID) to design an ultra-fast and low-power memory system. We develop a physics-based circuit-compatible model for CA-SQUID-based superconducting memristors (ScMs). Using this compact model, we design and test an ScM-based nonvolatile cryogenic memory system and explore the design space. Via analyzing the sensitivity and tunability of the device hysteresis up to the array level, we provide a comprehensive guideline for its experimental realization. The ScM-based memory system has the potential to solve the scalability issue of the state-of-the-art superconducting data storage systems and may trigger rapid advancement in quantum computing, space electronics, and cryogenic neuromorphic systems.