Serial Biasing Technique for Electronic Design Automation in RSFQ Circuits

Abstract

There has been renewed interest and efforts in increasing the complexity of superconductor circuits by means of electronic design automation (EDA). Serial biasing (SB) is a technique that reduces the total dc bias current required by large rapid single flux quantum (RSFQ) circuits, including its energy-efficient variant, ERSFQ. We believe SB needs to be incorporated in any EDA flow for large circuits. In SB, equally biased circuit blocks are placed on galvanically isolated islands and biased in series. SFQ pulses are transferred between islands by means of driver-receiver pairs (DRPs). The special current management technique, called the grapevine (GV) approach and introduced earlier, is used to handle the bias current flowing in and out of an island. In this article, we present all required layout primitives needed to implement SB for the IARPA-led SuperTools cell library that targets the SFQ5ee fab node at MIT Lincoln Laboratory. We discuss the horizontal and vertical composite driver-receiver pairs that comprise not only DRPs but also transmitters and receivers for passive transmission lines. We present the basic blocks to implement the GV managing technique for current injection and extraction. As a proof of concept, we designed a four-island test circuit that comprises all discussed layout primitives and employs an on-chip pseudorandom binary sequence generator as a test pattern source. The test circuit worked up to 50 GHz at the BER level of 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">−12</sup> . We discuss future steps to improve the SB technique.