Single Event Latchup Research Articles

Radiation Hardening of an SiGe BiCMOS Wilkinson ADC for Distributed Motor Controller Application

The radiation robustness of a newly designed Wilkinson analog-to-digital converter (ADC) is being investigated. The ADC is a front-end design block within a cold capable, analog sense, application-specific integrated circuit (ASIC) manufactured using the IBM 0.5 μm silicon germanium (SiGe) BiCMOS 5HP process. The ASIC is part of a next-generation, cold capable, distributed motor controller architecture, which is a candidate for the next generation of Mars rovers. Its main function is to interface with various sensor types to monitor motor health (i.e., temperature, mechanical stress, pressure). While relatively well-hardened against total ionizing dose and destructive single-event latchup, the ADC showed some SEU (SET) sensitivity that is heavily dependent on its input channel configuration. For this study, we used a combination of experiments (pulsed-laser) and Cadence mixed-mode SEE simulations to explain the heavy ion irradiation results. We concluded that ADC input impedance configuration should be carefully controlled in the design of radiation-hardened systems for space.

Fault-tolerant TMR and DMR circuits with latchup protection switches

The paper presents CMOS ASICs which can tolerate the single event upsets (SEUs), the single event transients (SET), and the single event latchup (SEL). Triple and double modular redundant (TMR and DMR) circuits in combination with SEL protection switches (SPS) make the base of the proposed approach. The SPS had been designed, characterized, and verified before it became a standard library cell. A few additional steps during logic synthesis and layout generation have been introduced in order to implement the redundant net-lists and power domains as well as to place the latchup protection switches. The approach and accompanying techniques have been verified on the example of a shift-register and a middleware switch processor.

A New Analyzing Method of Single Event Latch-Up Protection Circuit Based on Current Comparing and Its Performance Verification

Single event latch-up (SEL) is a significant issue for electronics design in space application, which would cause large currents in electronic devices, and may lead to burning out of devices. A new monitoring circuit based on current-comparing method is designed to protect the electronics away from SEL’s damage in radiation environment. The response time of protection circuit has been analyzed. The signal simulation results indicated that the operating time of the SEL protection circuit is dependent on the action time of current comparator and system application recovery time. The function of the monitoring circuit protection device away from SEL’s damage has validated through experiment at last.

Mechanism of multiple bit upsets induced by localized latch-up effect in 90 nm complementary metal semiconductor static random-access memory

By using the pulsed laser single effect facility, the single event upset and latch-up phenomenon are studied, and the bitmap of 90 nm complementary metal oxide semiconductor (CMOS) static random-access memory (SRAM) is mapped. It is shown that many multiple bit upsets occur and pulsed supply current of 20 mA amplitude is monitored. Based on the technology computer aided design (TCAD), it is found that the localized latch-up in CMOS SRAM is the main reason for the single event multiple bit upsets. Finally, by analyzing the results of the pulsed laser experiment and TCAD, it is found that the P/N well potential collapse is the key physical mechanism responsible for the spreading of the single event latch-up effect in 90 nm CMOS SRAM.

Single event latch-up effect and mitigation technique in different sized CMOS devices

Single event latch-up effect and mitigation technique in different sized CMOS devices

不同工艺尺寸CMOS器件单粒子闩锁效应及其防护方法

不同工艺尺寸CMOS器件单粒子闩锁效应及其防护方法

Single Event Effects in 4T Pinned Photodiode Image Sensors

This paper describes how Single Event Effects (SEEs) produced by heavy ions disturb the operation of Pinned Photodiode (PPD) CMOS Image Sensors (CISs) in the frame of space and nuclear applications. Several CISs with 4T and 5T pinned photodiode pixels were exposed to ions with a broad Linear Energy Transfer range (3.3 to 67.7 MeV·cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /mg). One sensor exhibited Single Event Latchups (SELs). Physical failure mechanism and latchup properties were investigated. SELs are caused by the level shifters of the addressing circuits, which create frame perturbations - following which, in some cases, parts of the addressing circuits need to be hardened. In the second part of the paper, the effects of anti-blooming capabilities on the Single Event Transient effects (SETs) are analyzed. SETs in pixels can be partially mitigated by anti-blooming through the transfer gate and/or a dedicated transistor. This work also shows that the number of pixels disturbed by SETs can be reduced by using appropriate anti-blooming techniques.

SEE Measurements and Simulations Using Mono-Energetic GeV-Energy Hadron Beams

Single Event Upset (SEU) measurements were performed on the ESA SEU Monitor using mono-energetic GeV-energy hadron beams available in the North Experimental Area at CERN. A 400 GeV proton beam in the H4IRRAD test area and a 120 GeV mixed pion and proton beam at the CERN-EU high Energy Reference Field facility (CERF) were used for this purpose. The resulting cross section values are presented and discussed as well as compared to the several hundred MeV case (typical for standard test facilities) from a physical interaction perspective with the intention of providing a more general understanding of the behavior. Moreover, the implications of the cross section dependence with energy above the several hundred MeV range are analyzed for different environments. In addition, analogous measurements are proposed for Single Event Latchup (SEL), motivated by discussed simulation results. Finally, a brief introduction of the future CHARM (CERN High-energy AcceleratoR Mixed facility) test installation is included.

SEL-UP: A CAD tool for the sensitivity analysis of radiation-induced Single Event Latch-Up

Space missions require extremely high reliable components that must guarantee correct functionality without incurring in catastrophic effects. When electronic devices are adopted in space applications, radiation hardened technology should be mandatorily adopted. In this paper we propose a novel method for analyzing the sensitivity with respect to Single Event Latch-up (SEL) in radiation hardened technology. Experimental results obtained comparing heavy-ion beam campaign demonstrated the feasibility of the proposed solution.

Transient device simulation of neutron-induced failure in IGBT: A first step for developing a compact predictive model

In atmospheric environment, neutron-induced single event effects are known to be a concern for electronic devices reliability. The effect of atmospheric radiation on integrated technologies (mainly single event upsets and latchup on CMOS) has been extensively investigated during the last 3 decades and testing standards have even been developed (e.g. JESD89a, IEC TS 62396). Moreover at present, a good knowledge of the physical mechanisms at stake allows to use efficient prediction tools which are now mature enough to be transferred to academic and industrial end-users [1,2]. Those tools are in particular useful to predict the expected failure rate of a given technology with very little technological knowledge.Atmospheric radiation-induced power devices failures are not treated as well. Even though numerous studies have been performed, no standard exist for testing devices in atmospheric environment. On the other hand, the complexity of the failure modes at play makes it very difficult to develop efficient prediction tools.In this paper, an analysis of the physical mechanisms at play is performed using 2D TCAD simulation tool. In particular, the sensitive region as well as the role of the temperature has been investigated. Moreover the simulated failure mode is compared to the phenomenological model described in the literature. The goal of this paper is to determine whether some simplifications in the triggering mode for a failure can be done in order to ease the development of analytical prediction tools.

New Testing Methodology of an Analog to Digital Converter for the LHC Mixed Radiation Field

In this work a commercial off the shelf Analog to Digital Converter (ADC), based on a Successive Approximation Register (SAR) structure, has been tested to verify Total Ionizing Dose (TID) effects and evaluate Single Event Upset (SEU) and Single Event Latch-up (SEL) cross sections. A well-known test is used to verify the SEU cross section with a constant input voltage; a new test method is proposed to measure the dynamic ADC performance, such as the Effective Number Of Bit (ENOB), continuously during the irradiation. The tests have been carried out at the Paul Scherrer Institute (PSI) beam facility at 230 MeV, at CERN in a dedicated experimental area that recreates the same radiation environment of the Large Hadron Collider (LHC) tunnel, and at a heavy ion facility, especially for defining the SEL risk.

Single-Event Effects in CMOS Image Sensors

In this paper, 3T active pixel sensors (APS) are exposed to heavy ions (N, Ar, Kr, Xe), and single-event effects (SEE) are studied. Devices were fully functional during exposure, no single-event latch-up (SEL) or single-event functional interrupt (SEFI) happened. However, single-event transient (SET) effects happened on frames: line disturbances, and half or full circular clusters of white pixels. The collection of charges in cluster was investigated with arrays of two pixel width (7 and 10 μm), with bulk and epitaxial substrates. This paper shows technological and design parameters involved in the transient events. It also shows that STARDUST simulation software can predict cluster obtained for bulk substrate devices. However, the discrepancies in epitaxial layer devices are large-which shows the need for an improved model.

SEL-Sensitive Area Mapping and the Effects of Reflection and Diffraction From Metal Lines on Laser SEE Testing

Laser and heavy-ion data reveal the areas and shapes of single-event latchup (SEL)-sensitive regions in CMOS test structures and their positions relative to the affected p-n-p-n paths. Contrary to previous two-dimensional studies, this three-dimensional study shows that the position of maximum SEL sensitivity in these structures is not centered on a p-n-p-n region, but between two neighboring p-n-p-n regions, suggesting that synergistic triggering increases SEL sensitivity. The SEL-sensitivity maps suggest that laser light scattered from metal lines toward the silicon can contribute to the SEE response, for both back-side-incident two-photon absorption and front-side-incident single-photon absorption laser tests. We describe the metallization configurations and laser pulse energies for which reflected and/or diffracted laser light may contribute to the single-event effect (SEE) response.

Single event effect characterization of the mixed-signal ASIC developed for CCD camera in space use

We present the single event effect (SEE) tolerance of a mixed-signal application-specific integrated circuit (ASIC) developed for a charge-coupled device camera onboard a future X-ray astronomical mission. We adopted proton and heavy ion beams at HIMAC/NIRS in Japan. The particles with high linear energy transfer (LET) of 57.9MeVcm2/mg is used to measure the single event latch-up (SEL) tolerance, which results in a sufficiently low cross-section of σSEL<4.2×10−11cm2/(Ion×ASIC). The single event upset (SEU) tolerance is estimated with various kinds of species with wide range of energy. Taking into account that a part of the protons creates recoiled heavy ions that have higher LET than that of the incident protons, we derived the probability of SEU event as a function of LET. Then the SEE event rate in a low-earth orbit is estimated considering a simulation result of LET spectrum. SEL rate is below once per 49years, which satisfies the required latch-up tolerance. The upper limit of the SEU rate is derived to be 1.3×10−3events/s. Although the SEU events cannot be distinguished from the signals of X-ray photons from astronomical objects, the derived SEU rate is below 1.3% of expected non-X-ray background rate of the detector and hence these events should not be a major component of the instrumental background.

Radiation Hardness Assurance Testing of Microelectronic Devices and Integrated Circuits: Test Guideline for Proton and Heavy Ion Single-Event Effects

This document gives detailed test guidelines for single-event upset (SEU), single-event latchup (SEL), single-event burnout (SEB), and single-event gate rupture (SEGR) hardness assurance testing. It includes guidelines for both heavy-ion and proton environments. The guidelines are based on many years of testing at remote site facilities and our present understanding of the mechanisms for single-event effects.

DC/DC 강압컨버터의 PWM-IC 제어기의 TID 및 SEL 실험

DC/DC 컨버터는 임의의 직류전원을 부하가 요구하는 형태의 직류전원으로 변환시키는 효율이 높은 전력변환기이다. DC/DC 컨버터는 PWM-IC(펄스폭 변조 집적회로) 제어기, MOSFET(산화물-반도체 전계 효과 트랜지스터), 인덕터, 콘덴서 등으로 구성되어있다. 코발트 60 (<TEX>$^{60}Co$</TEX>) 저준위 감마발생기를 이용한 TID실험에서 방사선의 영향으로 PWM-IC의 전기적 특성중에 문턱전압과 옵셋전압이 증가되고, SEL에 적용된 4종류의 중이온 입자는 PWM-IC의 파형을 불안정하게 만든다. 또한, 입/출력관계의 파형을 SPICE 시뮬레이션 프로그램으로 관찰하였다. PWM-IC의 TID 실험은 30 Krad 까지 수행하였으며, SEL 실험을 제어보드를 구현한 후 LET(<TEX>$MeV/mg/cm^2$</TEX>)별 cross section(<TEX>$cm^2$</TEX>)으로 연구하였다. DC/DC switching power converters are commonly used to generate a regulated DC output voltage with high efficiency. The DC/DC converter is composed of a PWM-IC (pulse width modulation-integrated circuit) controller, a MOSFET (metal-oxide semiconductor field effect transistor), inductor, capacitor, etc. It is shown that the variation of threshold voltage and the offset voltage in the electrical characteristics of PWM-IC increase by radiation effects in TID (Total Ionizing Dose) testing at the low energy <TEX>${\gamma}$</TEX> rays using <TEX>$^{60}Co$</TEX>, and 4 heavy ions applied for SEL (Single Event Latch-up) make the PWM pulse unstable. Also, the output waveform for the given input in the DC/DC converter is observed by the simulation program with integrated circuit emphasis (SPICE). TID testing on PWM-IC is accomplished up to the total dose of 30 krad, and the cross section(<TEX>$cm^2$</TEX>) versus LET(<TEX>$MeV/mg/cm^2$</TEX>) in the PWM operation is studied at SEL testing after implementation of the controller board.

Fault-tolerant ASIC: Design and implementation

The paper presents fault-tolerant CMOS ASICs which are immune to the single event upsets (SEU), the single event transients (SET), and the single event latchup (SEL). Triple and double modular redundant (TMR and DMR) circuits and SEL protection switches (SPS) make the base for a modified fault-tolerant ASIC design flow. The proposed design flow requires the standard design automation tools and a few additional steps during logic synthesis and layout generation. An extra step is necessary to generate the redundant design net-list including voters. Other two extra steps (definition of the redundant power domains and placement of the SPS) have to be performed in the layout phase. The concept has been proven by design and implementation of the two digital circuits: shift-register and synchronous counter.

PENGARUH GANGGUAN LINGKUNGAN ANTARIKSA PADA SISTEM ELEKTRONIK LAPAN-TUBSAT (EFFECT OF SPACE ENVIRONMENT DISTURBANCE IN LAPAN-TUBSAT SATELLITE)

LAPAN-TUBSAT has been operated more than five years. During the operation, LAPAN-TUBSAT faces several anomaly. It could be observed by using real time telemetry and long time telemetry. When and where an anomaly appeared can be detected with long time telemetry. Anomaly event on LAPAN-TUBSAT’s PCDH is caused by Single Event Latch-Up (SEL) that happen in scale of weeks.These conditions required LAPAN-TUBSAT operators to take action in order to make LAPAN-TUBSAT back to normal operation. This paper describes statistic of SEL that occur in LAPAN-TUBSAT. Almost 70% of SEL event take place at South Atlantic Anomaly (SAA) and the rest at polar.&#x0D; Keywords: SEL, LAPAN-TUBSAT, Real time telemetry, Long time telemetry, PCDH

Effectiveness of SEL Hardening Strategies and the Latchup Domino Effect

Heavy ion, neutron, and laser experimental data are used to evaluate the effectiveness of various single event latchup (SEL) hardening strategies, including silicon-on-insulator (SOI), triple well, and guard rings. Although SOI technology is widely reported to be immune to SEL, conventional pnpn latchup can occur and has been observed in non-dielectrically isolated SOI processes. Triple well technologies are shown to be more robust against SEL than dual well technologies under all conditions used in this study, suggesting that the introduction of a deep N-well is an excellent zero-area-penalty hardening strategy. A single guard ring is shown to be sufficient for SEL immunity in the 180 nm CMOS technology investigated, and is likely sufficient for more modern CMOS technologies. After triggering latchup in a certain pnpn region, latchup was observed to spread to neighboring pnpn regions, which then infected other more distant regions until it had spread over a total distance of 700 micrometers. We discuss the physical mechanism of this latchup domino effect and its implications for device characterization and hardness assurance.

Certification of Parts for Space With the Variable Depth Bragg Peak Method

The Variable Depth Bragg Peak (VDBP) method uses long-range high-energy heavy ions to measure the Single Event Effect (SEE) cross-section as a function of linear energy transfer (LET(Si)) for commercially packaged integrated circuits with sensitive volumes at unknown depths. This is done by lowering the energy of the ions incident on the device-under-test (DUT) in steps, by insertion of polyethylene degraders of increasing thickness, until the maximum event cross-section is observed, which indicates that ions with the highest average LET(Si) (at the peak of the Bragg Peak) are depositing energy in the sensitive volume. The present paper describes use of the VDBP method to test for single event latchup (SEL) in packaged parts that do and do not fail catastrophically and to certify a device by assuring that every depth in the packaged device is exposed to a fluence of ions with average LET(Si) values greater than a specified value, in this case 60 MeV/mg/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .