Single Event Burnout Research Articles

Radiation damage in GaN/AlGaN and SiC electronic and photonic devices

The wide bandgap semiconductors SiC and GaN are commercialized for power electronics and for visible to UV light-emitting diodes in the case of the GaN/InGaN/AlGaN materials system. For power electronics applications, SiC MOSFETs (metal–oxide–semiconductor field effect transistors) and rectifiers and GaN/AlGaN HEMTs and vertical rectifiers provide more efficient switching at high-power levels than do Si devices and are now being used in electric vehicles and their charging infrastructure. These devices also have applications in more electric aircraft and space missions where high temperatures and extreme environments are involved. In this review, their inherent radiation hardness, defined as the tolerance to total doses, is compared to Si devices. This is higher for the wide bandgap semiconductors, due in part to their larger threshold energies for creating defects (atomic bond strength) and more importantly due to their high rates of defect recombination. However, it is now increasingly recognized that heavy-ion-induced catastrophic single-event burnout in SiC and GaN power devices commonly occurs at voltages ∼50% of the rated values. The onset of ion-induced leakage occurs above critical power dissipation within the epitaxial regions at high linear energy transfer rates and high applied biases. The amount of power dissipated along the ion track determines the extent of the leakage current degradation. The net result is the carriers produced along the ion track undergo impact ionization and thermal runaway. Light-emitting devices do not suffer from this mechanism since they are forward-biased. Strain has also recently been identified as a parameter that affects radiation susceptibility of the wide bandgap devices.

Low-Energy Ion-Induced Single-Event Burnout in Gallium Oxide Schottky Diodes

Low-energy ion-induced breakdown and single-event burnout are experimentally observed in β-Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> Schottky diodes with voltages well below those of expected electrical breakdown. Fundamentally different responses were observed among alpha-particle, Cf-252, and heavy-ion irradiation. TCAD simulations suggest that ion-induced burnout can be triggered at high voltages as a result of a single ion strike, leading to impact ionization, voltage-induced charge separation accentuated by the low intrinsic hole mobility in β-Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> , and breakdown. At significantly lower voltages, the cumulative buildup of displacement-damage-induced defects in β-Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> during high-fluence ion irradiation can lead to defect-driven breakdown due to the generation and motion of negatively charged Ga vacancies and O interstitials. First-principles calculations show that defect clusters can be formed that are much less resistive than the surrounding material. These clusters can be driven deeply into the device by the reverse bias, ultimately forming conduction paths that can facilitate the destruction of the device at reduced voltages.

Impact of Heavy-Ion Range on Single-Event Effects in Silicon Carbide Power Junction Barrier Schottky Diodes

Experimental heavy-ion responses of SiC Junction Barrier Schottky (JBS) diodes are presented. Measured data indicate that heavy ions having range less than the epitaxial thickness do not cause degradation or catastrophic failure, even with the device biased above the rated breakdown voltage. Measured data also indicate that when the heavy ions have range longer than the epitaxial layer thickness, the devices exhibit degradation as single-event leakage current (SELC), as well as catastrophic single-event burnout (SEB) at biases less than half of the rated breakdown voltage. Device failure was observed when irradiating with high-energy ions having long ranges, but not when irradiating with low-energy ions that stop in the epitaxial layer. Mechanisms of observed heavy-ion effects are examined with TCAD device modeling.

Mono-Energetic Proton Induced Damages in SiC Power MOSFETs

The mechanisms of single event burnout (SEB) are investigated for SiC MOSFETs by proton irradiation with varying energies. The material melting due to thermal runaway is observed at the damage region for the device with SEB. The proton energy is proved to be a key factor to affect SEB. The proton induced SEB cross-section is higher for higher energy proton irradiation. The information of the secondary ions is obtained through Monte Carlo simulations to explain this phenomenon. The occurrence of SEB depends on the LET value and range of the secondary ions. The relations between SEB and quasi-stationary avalanche characteristics for SiC MOSFET are verified by TCAD simulations. SEB phenomenon actually origins from the secondary breakdown caused by charged ion injection. So the drain bias voltage during irradiation is very important to determine whether SEB occurs.

Effect of Biased Field Rings to Improve Charge Removal after Heavy-Ion Strikes in Vertical Geometry β-Ga2O3 Rectifiers

In this study, the response to a heavy-ion strike and the resulting single effect burnout on beta-Ga2O3 Schottky diodes with biased field rings is investigated via TCAD. The model used to simulate the device under high-reverse bias is validated using experimental current-voltage (I-V) curves. A field ring configuration for the device demonstrates an improved charge removal after simulated heavy-ion strikes. If the time scale for charge removal is faster than single event burnout, this can be an effective mechanism for reducing the effect of single ion strikes. This study explores various configurations of the termination structure and shows the impact of different design parameters in terms of a transient response after the ion strike.

Simulation study on single-event burnout reliability of 4H-SiC trench gate MOSFET with combined P-buried layer

In this article, the purpose of this numerical study is to investigate the rated 3.3-kV SiC power gate trench MOSFET structure with ground and float p-buried layer (DGF-MOS). The simulation results show the introduction of ground and float p-buried layer and upper drift layer optimized breakdown voltage (BV) the specific on-resistance (Ron,sp), and gate drain charge (Qgd,sp), thus the figure of merit (BV2/Ron,sp) is improved by 130 % and the figure of merit (Ron,sp × Qgd,sp) is reduced 173 % compared with the conventional SiC power gate trench MOSFET (CT-MOS). Additionally, the single-event burnout (SEB) simulation results show that the critical degradation threshold of CT-MOS structure is 900 V at LET = 0.5 pC/μm. The robustness of the DGF-MOS structure design to heavy ions was simulated. The results show that the maximum temperature peaks around the gate trench and substrate junction of the DGF-MOS structure could both be effectively suppressed due to the decrease in electric field peak. Consequently, the DGF-MOS structure showed a severe denaturation threshold of 1500 V, which was 66.6 % higher than that of the CT-MOS structure.

New insight into gain suppression and single event Burnout effects in LGAD

Low Gain Avalanche Detectors (LGADs) will be employed in the CMS MTD and ATLAS HGTD upgrades to mitigate the high levels of pile-up events expected in the High Luminosity phase of the LHC. Over the last several years, much attention has been focused on designing radiation-tolerant gain implants to ensure that these sensors survive the expected fluence (>1015 neq/cm2). This work reports several effects observed during our previous studies on two relevant phenomena Single Event Burnout (SEB) and carrier density-induced Gain Suppression (GS). Influence of irradiation level, pad configuration and gain layer depth on SEB are discussed. In this paper, we also extend GS study with a new insight into the spatio-temporal dynamics of charge transport in LGAD, probed with a focused ion beam.

Single-event burnout hardening evaluation with current and electric field redistribution of high voltage LDMOS transistors based on TCAD Simulations

—A single-event burnout (SEB) hardened design based on high voltage lateral double-diffused metal-oxide-silicon (LDMOS) devices with an optimal partial buried oxide (BOX) layer and a N-buffer layer is firstly proposed in this paper. By analyzing the response of surface electric field and transient current, the optimal parameters of hardened layers are selected. Simulation results reveal that an optimal buffer layer can suppress the peak electric field from 4.5 MV/cm to 2 MV/cm, recreate the position of peak electric field and an optimal BOX layer can reconstruct the path of electron and hole currents, reducing the risk of parasitic bipolar-junction-transistor (BJT). By contrast, the SEB triggering voltage can be improved from 197 V to 396 V, with an increase of 100%. And the ratio of safe operating area (SOA) with SEB to breakdown voltage (BV) can be increased from 30% to 69%. In the case of heavy-ions with different energies, the SEB hardened LDMOS also has better performance than the conventional one.

A Fault-Tolerant Strategy for Three-Level Flying-Capacitor DC/DC Converter in Spacecraft Power System

With the development of space exploration, high-power and high-voltage power systems are essential for future spacecraft applications. Because of the effects of space radiation such as single event burnout (SEB), the rated voltage of power devices in converters for a spacecraft power system is limited to a level much lower than that for traditional ground applications. Thus, multi-level DC/DC converters are good choices for high-voltage applications in spacecraft. In this paper, a fault-tolerant strategy is proposed for a three-level flying capacitor DC/DC converter to increase the reliability with minimal cost. There is no extra hardware needed for the proposed strategy; the fault tolerance of the converter is only achieved by changing the software control strategy. A stage analysis of the proposed strategy is provided in detail for different fault locations and ratios between the input and output voltage. Finally, a simulation model and prototype are built to verify the effectiveness of the proposed strategy.

Heavy ion single event effect in double-trench SiC metal-oxide-semiconductor field-effect transistors

In this paper, experiments on 208 MeV Ge ion irradiation with different source-drain bias voltages are carried out for the double-trench SiC metal–oxide–semiconductor field-effect transistors, and the physical mechanism of the single event effect is analyzed. The experimental results show that the drain leakage current of the device increases more obviously with the increase of the initial bias voltage during irradiation. When the bias voltage is 400 V during irradiation, the device has a single event burned at a fluence of 9×10&lt;sup&gt;4&lt;/sup&gt; ion/cm&lt;sup&gt;2&lt;/sup&gt;, and when the bias voltage is 500 V, the device has a single event burned at a fluence of 3×10&lt;sup&gt;4&lt;/sup&gt; ion/cm&lt;sup&gt;2&lt;/sup&gt;, so when the LET value is 37.3 MeV·cm&lt;sup&gt;2&lt;/sup&gt;/mg, the SEB threshold of DUT does not exceed 400 V, which is lower than 34% of the rated operational voltage. The post gate-characteristics test results show that the leakage current of the device with a bias voltage of 100 V does not change significantly during irradiation. When the bias voltage is 200 V, the gate leakage and the drain leakage of the device both increase, so do they when the bias voltage is 300 V, which is positively related to bias voltage. In order to further analyze the single particle effect mechanism of device, the simulation is conducted by using TCAD tool. The simulation results show that at low bias voltage, the heavy ion incident device generates electron-hole pairs, the electrons are quickly swept out, and the holes accumulate at the gate oxygen corner under the effect of the electric field, which combines the source-drain bias voltage, leading to the formation of leakage current channels in the gate oxygen layer. The simulation results also show that at high bias voltage, the electrons generated by the incident heavy ion move towards the junction of the N&lt;sup&gt;–&lt;/sup&gt; drift layer and the N&lt;sup&gt;+&lt;/sup&gt; substrate under the effect of the electric field, which further increases the electric field strength and causes significant impact ionization. The local high current density generated by the impact ionization and the load large electric field causes the lattice temperature to exceed the melting point of silicon carbide, causing single event burnout. This work provides a reference and support for studying the radiation effect mechanism and putting silicon carbide power devices into aerospace applications.

Research of Single-Event Burnout in 1.2-kV Rated CoolSiC Trench MOSFET

This paper presents the two-dimensional (2-D) numerical simulation results of heavy-ion induced reverse drain current degradation and single-event burnout (SEB) in the 1.2-kV rated CoolSiC Trench metal-oxide-semiconductor field-effect transistor (MOSFET). The physics models employed in simulations and critical failure conditions were validated by the heavy-ion irradiation experiments of the commercially available 1.2-kV rated SiC planar-gate MOSFET devices. The CoolSiC Trench MOSFET was proven to behave comparative SEB performance compared with the SiC planar-gate MOSFET. The robustness of the CoolSiC Trench MOSFET with different single buffer layer (SBL) designs against a heavy ion was simulated. Furthermore, the SBL-CoolSiC Trench MOSFET with low carrier lifetime control was investigated. According to the simulation results, the severe degeneration failure tolerance increased to 800 V; the SEB failure tolerance could reach 900 V.

A compact circuit-level model for single-event burnout in SiC power MOSFET devices

This paper presents a compact circuit-level model for single-event burnout (SEB) in silicon carbide (SiC) metal-oxide field-effect transistors (MOSFETs). Key parameters of the equivalent circuit model of the MOSFET are analyzed and determined in detail, including nonlinear parasitic drain-source capacitance and nonlinear parasitic gate-drain capacitance. The effect of the parasitic bipolar junction transistor is considered and an iteratively optimized double-exponential current source is used to simulate the transient power current generated by incident heavy ions. The equivalent circuit model of the MOSFET is verified by comparing the SPICE simulation curves, TCAD simulation curves, and the curves in the SiC power double trench MOSFET’s datasheet (SCT3080KL). Then, the SEB is caused by heavy ions at various incident positions, linear energy transfer values, drain-source voltage (V ds), and gate-source voltage (V gs) using the TCAD and HSPICE simulations. Simulation results on the SPICE model coincide with the TCAD simulation results. Moreover, this compact model is used to predict the SEB threshold for devices with higher breakdown voltage ratings.

A Single-Event Burnout Hardened Super-Junction Trench SOI LDMOS with Additional Hole Leakage Paths

In this paper, a novel super-junction trench silicon-on-insulator laterally-diffused metal-oxide-semiconductor (SJT SOI LDMOS) power device with additional hole leakage paths to improve single-event burnout (SEB) performance under high liner energy transfer (LET) is proposed for the first time. The electrical characteristics and SEB performance of the proposed SJT SOI LDMOS are both enhanced effectively. The replacement of a lightly doped N drift region with a heavily doped P pillar and N pillar considerably improves the tradeoff between breakdown voltage (BVDS) and specific on-resistance (Ron,sp). Compared with the conventional trench SOI LDMOS (CT SOI LDMOS), the static figures of merit (FOM, BVDS2/Ron,sp) of the SJT SOI LDMOS increases by 239%. The SEB performance of the SJT SOI LDMOS is significantly improved as the holes induced by the heavy ion can be quickly absorbed to the trench source metal through the heavily doped P+ region and P buried region rather than the base resistor of the parasitic bipolar junction transistor (BJT). The SEB threshold voltage (VSEB) of the CT SOI LDMOS is 58 V (39% of the BVDS) and that of the SJT SOI LDMOS is up to 173 V (87% of the BVDS) at high LET of 1 pC/μm.

TCAD evaluation of single-event burnout hardening design for SiC Schottky diodes

In this paper, a single-event burnout (SEB) hardening technique for Schottky diodes at a linear energy transfer (LET) value of 0.5 pC/μm (75.5 MeV/mg/cm2) is presented and investigated by 2-D numerical simulations. The simulation results show that, when compared with the conventional junction barrier Schottky (JBS) diode with multiple buffer layers, the proposed structure can significantly reduce the electric field at the metal/SiC interface with the help of the trench, thereby reducing the interface temperature. Moreover, the maximum global temperature of the proposed structure is also reduced. The maximum global temperature of the proposed structure is 1989 K and the temperature at the Schottky contact interface is 439 K for the bias voltage of 1000 V and LET value of 0.5 pC/μm (75.5 MeV/mg/cm2) which shows that the new structure has better SEB performance. In addition, the hardening method proposed in this paper can be applied at different breakdown voltages by adjusting the structural parameters of the device.

Design and testing of LGAD sensor with shallow carbon implantation

The low gain avalanche detectors (LGADs) are thin sensors with fast charge collection which in combination with internal gain deliver an outstanding time resolution of about 30 ps for Minimum Ionizing Particles (MIP). High collision rates and consequent large particle rates crossing the detectors at the upgraded Large Hadron Collider (LHC) in 2028 will lead to radiation damage and deteriorated performance of the LGADs. The main consequence of radiation damage is loss of gain layer doping (acceptor removal) which requires an increase of bias voltage to compensate for the loss of charge collection efficiency and consequently time resolution. The Institute of High Energy Physics (IHEP), Chinese Academy of Sciences (CAS) has developed a process based on the Institute of Microelectronics (IME), CAS capability to enrich the gain layer with carbon to reduce the acceptor removal effect by radiation. After 1 MeV neutron equivalent fluence of 2.5 × 1015 neq/cm2, which is the maximum fluence to which sensors will be exposed at ATLAS High Granularity Timing Detector (HGTD), the IHEP-IME second version (IHEP-IMEv2) 50μm LGAD sensors already deliver adequate charge collection >4 fC and time resolution <50 ps at voltages <400 V. The operation voltages of these 50μm devices are well below those at which single event burnout may occur.

Single-event burnout hardening of RC-IGBT with the raised N-buffer layer

This paper proposes a reverse conducting insulated gate bipolar transistors (RC-IGBT) structure with a raised N-buffer layer (RNB-IGBT) to improve the single-event burnout (SEB) robustness. The electrical and radiation properties of the structure were verified by TCAD simulations. At the same snapback voltage of 0.22 V and the liner energy transfer (LET) of 60 MeVcm2/mg conditions, the SEB threshold of RNB-IGBT is improved by 52 % compared to that of conventional RC-IGBT. This result indicates that the raised N-buffer layer of the RNB-IGBT can effectively reduce impact ionization, so it can suppress excessive heat concentration and avoid induce SEB.

Comprehensive study of the radiation effects on the LDMOS transistors

The reliability of power devices is attracting more and more attention, especially in the extreme radiation environment. The laterally diffused metal–oxide–semiconductor (LDMOS) has been widely used in high voltage integrated circuits. In this paper, the radiation effects of LDMOS transistors are extensively investigated through three-dimensional (3D) TCAD simulations, including Total-Ionizing Dose (TID), Single-Event Effect (SEE) and Transient Dose Rate Effect (TDRE). Firstly, the mechanism of TID effect on the LDMOS is revealed in consideration of temperature variations. Secondly, the single-event effect of the LDMOS is studied with different incident positions, linear energy transfer (LET) values, incident lengths, incident angles, bias conditions and temperatures. Besides, the combined effect of total-ionizing dose and single-event burnout is characterized. Finally, transient response of the LDMOS under transient γ radiation is also studied comprehensively. Therefore, it gives an insight into the physical mechanisms and response characteristics of complex radiation effects, which can provide guidance for radiation-hardened by design and application of the LDMOS devices.

Single-event burnout of LDMOS with polygon P+ structure

The performance and triggering mechanism of the single-event burnout (SEB) of the lateral double diffused MOSFET with polygon P+ insert structure (PP-LDMOS) are evaluated by 2-D numerical simulations. The novel PP-LDMOS and the conventional LDMOS are analyzed and compared to examine the effect of the polygon P+ insert structure on the SEB performance of the LDMOS device. The most sensitive volume of the conventional LDMOS and PP-LDMOS are investigated. In addition, the hardening mechanism of PP-LDMOS is explained. The simulation results show that the polygon P+ structure can discharge the holes generated by the ion's strike effectively. Compared with the conventional LDMOS structure, the polygon P+ insert structure can improve the SEB threshold voltage from 19 % to 88 % of breakdown voltage.

Charge deposition analysis of heavy-ion-induced single-event burnout in low-voltage power VDMOSFET

The heavy-ion-induced single-event burnout (SEB) risk in power MOSFETs (metal-oxide-semiconductor field-effect transistors) can be assessed in ground facilities, although it is costly and time-demanding. For this reason, there have been few experimental studies dedicated to investigate the relevant parameter related to the description of ion-induced SEB phenomenon. In this work the heavy-ion-induced SEB in a low-voltage power VDMOSFET (vertical double-diffused MOSFET) is studied using several ion-energy combinations. A self-consistent statistical analysis is carried out in order to elucidate the relationship between charge deposition and SEB triggering. Experimental data is compared to a predictive model from the literature for SEE (single-event effect) worst-case prediction in power MOSFETs, supporting for the first time its relevance to the worst-case prediction in the SEB mechanism.

Comparison in radiation tolerance between FLR planar junction termination and positive bevel edge termination for power diodes

In this paper, a coupled electro-thermal simulation model is established to investigate the single event burnout (SEB)-induced failure in power diode. The radiation tolerance of the two different termination structures, the field limiting ring (FLR) planar junction termination and the positive bevel edge termination, is revealed comparatively. Firstly, through the comparison in the SEB threshold voltage, our simulation results indicate that the positive bevel edge termination exhibits a stronger robustness to SEB. The difference in the anti-radiation performance can even reach 29.02% under the same ion incidence condition. Then, to fully understand why there is such a large difference in the radiation tolerance, we observed the entire failure process and obtained the SEB mechanism for the two termination structures. For the FLR planar junction termination, the edge of the main junction is the most sensitive region to SEB, since the high electric field here caused by the junction curvature effect can easily lead to the strong carrier multiplication and a large localized current density. By contrast, for the positive bevel edge termination, the electric field can be effectively reduced along the beveled surface, therefore, there is no electric field crowding at the edge of the pn junction. As a result, the positive bevel edge termination naturally exhibits a superior anti-radiation performance compared to the FLR planar junction termination structure.