Single-ended RF Research Articles

240 Gbit/s Silicon Photonic Mach-Zehnder Modulator Enabled by Two 2.3-Vpp Drivers

We recently reported for the first time 200 Gbit/s/ $\lambda$ net rate data transmission with a single silicon photonic modulator in an intensity modulation direct detection link. Our demonstration relied on an in-house designed, O-band segmented-electrode MZM. In this article, we detail the optimization of the modulator driving scheme, bandwidth/efficiency trade-off and modulation format enabling this result. We use two single-ended RF signals, each having 2.3-Vpp amplitude only, to drive two 1.5-mm modulator segments and transmit data at 80 Gbaud PAM-8 (240 Gbit/s) across 2 km under the 20% soft-decision forward error correction BER threshold of 2E-02. We further decrease the BER using maximum likelihood sequence detection (MLSD), and discuss the related implications. Additionally, we present the system margins regarding modulator drive voltage, received optical power and equalizer taps. At 240 Gbit/s line rate, the modulator energy consumption is only 73 fJ/bit at the SD-FEC threshold. We finally discuss practical implementation considerations for our system.

A RF PVT Compensated Negative Resistance Circuit for Q-factor Improvement of Passive Elements in CMOS

A RF process, voltage and temperature (PVT) compensated negative resistance (NR) circuit is proposed to improve the quality factor (Q-factor) of CMOS passive devices while ensuring stability over PVT variations. It is implemented in the form of a grounded NR circuit to support single-ended RF circuit applications. Various circuit techniques such as a diode-connected load, a proportional-to-absolutetemperature (PTAT) current source and an adaptive body-biasing based threshold voltage compensation have been adopted to obtain a stable negative resistance value. Simulation results show that the Qfactor of on-chip spiral inductors loaded by the proposed NR circuit is improved from 6 to 60 at 1 ㎓ under typical corner conditions (tt, 1.2V, 27 ℃). The simulated Q-factor variation in corner conditions is approximately 37, which is approximately 6.5 times more stable than conventional NR circuit without compensation.

Design of Self-Differential Down-Conversion I/Q Mixer for 2.4 GHz IoT Application

A 2.4 GHz self-differential down-conversion Gilbert cell mixer with current-reuse topology is presented in this paper. This design is targeted for low-power IoT applications. Here, by using a novel self-differential RF input stage with current-reuse topology, the single-ended RF signal can be transferred into differential signals without using a balun. With an applied local oscillator (LO) power of 10 dBm and RF signal of -30 dBm, this mixer demonstrates 9.886 dB of conversion gain, 10.4 dB of noise figure at 5 MHz and an IIP3 of 1.1767dBm in both I/Q branch. The design consumes 1.57 mA from a 1.8 V voltage supply.

Hitting the Sweet Spot: A Single-Ended Power Amplifier Exploiting Class AB Sweet Spots and Optimized Third Harmonic Termination

The single-ended RF power amplifier (PA) is a standard design approach in the RF engineer?s tool kit, but high efficiency and good linearity may only be achieved if the harmonic terminations and biasing conditions are carefully examined. This is demonstrated in a single-ended PA using class-AB sweet spots and an optimized third harmonic termination, which won first place at the 2016 IEEE Microwave Theory and Techniques Society (MTT-S) International Microwave Symposium?s high-efficiency PA student design competition, sponsored by Technical Committee MTT-5.

A 2.4-GHz CMOS Class-E Synchronous Rectifier

A class-E synchronous rectifier has been designed and implemented using 0.13- $\mu {\text {m}}$ CMOS technology. A design methodology based on the theory of time-reversal duality has been used where a class-E amplifier circuit is transformed into a class-E rectifier circuit. The methodology is distinctly different from other CMOS RF rectifier designs which use voltage multiplier techniques. Power losses in the rectifier are analyzed including saturation resistance in the switch, inductor losses, and current/voltage overlap losses. The rectifier circuit includes a 50- $\Omega $ single-ended RF input port with on-chip matching. The circuit is self-biased and completely powered from the RF input signal. Experimental results for the rectifier show a peak RF-to-dc conversion efficiency of 30% measured at a frequency of 2.4 GHz.

A 40-MHz-to-1-GHz Fully Integrated Multistandard Silicon Tuner in 80-nm CMOS

To address a worldwide market, silicon tuners have to support a wide range of frequencies and standards, motivating the use of architectures inspired by the software-defined-radio paradigm. DVB-T, DVB-C, ATSC-A/74 as well as cable modems (DOCSIS) and analog TV require low-noise, high-linearity front-ends with high-performance local oscillators. Integrability and cost dictate minimization of external components. Unlike common approaches [1,2], the silicon tuner presented in this paper features one single-ended RF input for the entire 40MHz-to-1GHz band, requires no external SAW filters or balun, and supports channel bandwidths from 5 to 8MHz. The analog IF output is programmable from 5MHz to 44MHz, supporting both modern digital demodulators and legacy analog demodulators. The receiver uses a low-IF architecture and is able to process the broadband input spectrum through the combination of a low-noise programmable RF filter, a digitally calibrated harmonic-rejection mixer, and a wide dynamic range ADC, whose intrinsic filtering nature and large SNDR make the tuner compatible with the very demanding ATSC A/74 standard. The chip's sophisticated digital back-end provides channel filtering and image rejection for the signal path, runs the RF and IF AGCs, and controls a variety of calibration schemes used to improve performance and robustness toward PVT variations. The chip has been designed in a scaled 90nm CMOS technology, requires a 1.8V analog supply and a 1.0V digital supply, and dissipates <450mW during normal operation and <10mW in standby mode. The BoM is limited to a single LNA bias inductor and a 40MHz crystal, thus minimizing the required footprint and cost.

A BiCMOS single ended multiband RF-amplifier and mixer with DC-offset and second order distortion suppression

Direct conversion receivers are widely used for full duplex mobile radio communication systems. This paper describes a novel SAW-less single-ended RF amplifier connected to a single-ended mixer with a feedback loop that suppresses the second-order distortion from TX cross modulation of the LO-leakage as well as DC-offset at the mixer output. In Monte Carlo simulations the design achieves +47 dBm minimum IIP2 with 32 dB conversion voltage gain. The advantage with the proposed architecture is that it is fully single-ended. Especially in multiband integrated radios this is highly desirable since the pin-count for the LNAs is reduced by half. The PCB routing of the RF input signal is simplified. The design requires two off-chip filter capacitors of non critical value intended to be placed on the laminate inside the package.

Ku-band SiGe HBT I/Q subharmonic mixer with reactive quadrature generators

This article demonstrates a high-frequency 0.35-μm SiGe HBT subharmonic downconverter with reactive in-phase and quadrature-phase (I/Q) generators.Two reactive I/Q generators are integrated in our work to provide differential quadrature RF and LO signal. The I/Q subharmonic downconverter with single-ended LO, RF, and IF (I/Q) ports has a conversion gain of 1 dB, IP1dB of −10 dBm, IIP3 of 0 dBm, and IIP2 of 21 dBm at 16.4 GHz. The magnitude and phase errors between the I and Q channels are 1.34% and 0.6°, respectively. The dc power consumption of this I/Q mixer without output buffers is approximately 5 mW. © 2010 Wiley Periodicals, Inc. Microwave Opt Technol Lett 52: 1516–1520, 2010; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.25281

A 65 nm CMOS 30 dBm Class-E RF Power Amplifier With 60% PAE and 40% PAE at 16 dB Back-Off

A 30 dBm single-ended class-E RF power amplifier (PA) is fabricated in a baseline 65 nm CMOS technology. The PA is constructed as a cascode stage formed by a standard thin-oxide device and a dedicated novel high voltage extended-drain thick-oxide device. Both devices are implemented without using additional masks or processing steps. The proposed PA uses an innovative self-biasing technique to ensure high power-added efficiency (PAE) at both high output power (P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">out</sub> ) and power back-off levels. At 2 GHz, the PA achieves a PAE of 60% at a Pout of 30 dBm and a PAE of 40% at 16 dB back-off. Stress tests indicate the reliability of both the novel high voltage device and the design.

A Single-Ended Fully Integrated SiGe 77/79 GHz Receiver for Automotive Radar

A single-ended 77/79 GHz monolithic microwave integrated circuit (MMIC) receiver has been developed in SiGe HBT technology for frequency-modulated continuous-wave (FMCW) automotive radars. The single-ended receiver chip consists of the first reported SiGe 77/79 GHz single-ended cascode low noise amplifier (LNA), the improved single-ended RF double-balanced down-conversion 77/79 GHz micromixer, and the modified differential Colpitts 77/79 GHz voltage controlled oscillator (VCO). The LNA presents 20/21.7 dB gain and mixer has 13.4/7 dB gain at 77/79 GHz, and the VCO oscillates from 79 to 82 GHz before it is tuned by cutting the transmission line ladder, and it centres around 77 GHz with a tuning range of 3.8 GHz for the whole ambient temperature variation range from -40degC to +125degC after we cut the lines by tungsten-carbide needles. Phase noise is -90 dBc/Hz@l MHz offset. Differential output power delivered by the VCO is 5 dBm, which is an optimum level to drive the mixer. The receiver occupies 0.5 mm2 without pads and 1.26 mm2 with pads, and consumes 595 mW. The measurement of the whole receiver at 79 GHz shows 20-26 dB gain in the linear region with stable IF output signal. The input P1dB of the receiver is -35 dBm.

&lt;/title&gt; &lt;/titles&gt; &lt;publication_date&gt; &lt;month&gt;06&lt;/month&gt; &lt;year&gt;2007&lt;/year&gt; &lt;/publication_date&gt; &lt;pages&gt; &lt;first_page&gt;679&lt;/first_page&gt; &lt;last_page&gt;680&lt;/last_page&gt; &lt;/pages&gt; &lt;publisher_item&gt; &lt;item_number item_number_type='arNumber'&gt;4200994&lt;/item_number&gt; &lt;/publisher_item&gt; &lt;doi_data&gt; &lt;doi&gt;10.1109/TIM.2007.895578&lt;/doi&gt; &lt;resource&gt;http://ieeexplore.ieee.org/lpdocs/epic03/wrapper.htm?arnumber=4200994&lt;/resource&gt; &lt;/doi_data&gt; &lt;/journal_article&gt; &lt;journal_article&gt; &lt;titles&gt; &lt;title&gt;&lt;![CDATA[Measuring Nonlinear Differential RF Amplifiers Using One Single-Ended Source

A measurement procedure for the nonlinear baseband response of a differential amplifier is proposed using the large-signal network analyzer. The setup uses only one single-ended RF generator. A simplified nonparametric model for the frequency response of the device and its nonlinear contributions over a wide power range is proposed, measured, and validated experimentally

A Monolithic SiGe Heterojunction Bipolar Transistor Gilbert Upconverter with Inductor–Capacitor Current Mirror Load and Lumped-Element Rat-Race Balun

A 5.2 GHz upconversion Gilbert mixer with single-ended intermediate frequency (IF), local oscillator (LO), and RF ports is demonstrated using 0.35 µm SiGe heterojunction bipolar transistor (HBT) technology. The upconverter has a single-ended IF port. In addition, a lumped-element rat-race hybrid is inserted in the LO input stage to maintain balanced LO signals. The physics of the lumped-element rat-race is discussed in this paper. A passive LC current mirror is used to convert the mixer's differential outputs into a single-ended output and double the output current. The design methodology of the LC current mirror and a new approach to improve the power gain with the output buffer are developed in this paper. The fully matched Gilbert upconverter has the conversion gain of -1 dB, OP1 dB of -10 dBm and OIP3 of 6 dBm when input IF=300 MHz, LO=4.9 GHz and output RF=5.2 GHz. The LO-IF isolation is -36 dB and the LO-RF isolation is -39 dB. The supply voltage is 3.3 V, the current consumption is 11.5 mA, and the die size is 0.98×0.83 mm2 with six integrated on-chip inductors.