A 40-MHz-to-1-GHz Fully Integrated Multistandard Silicon Tuner in 80-nm CMOS

Abstract

To address a worldwide market, silicon tuners have to support a wide range of frequencies and standards, motivating the use of architectures inspired by the software-defined-radio paradigm. DVB-T, DVB-C, ATSC-A/74 as well as cable modems (DOCSIS) and analog TV require low-noise, high-linearity front-ends with high-performance local oscillators. Integrability and cost dictate minimization of external components. Unlike common approaches [1,2], the silicon tuner presented in this paper features one single-ended RF input for the entire 40MHz-to-1GHz band, requires no external SAW filters or balun, and supports channel bandwidths from 5 to 8MHz. The analog IF output is programmable from 5MHz to 44MHz, supporting both modern digital demodulators and legacy analog demodulators. The receiver uses a low-IF architecture and is able to process the broadband input spectrum through the combination of a low-noise programmable RF filter, a digitally calibrated harmonic-rejection mixer, and a wide dynamic range ADC, whose intrinsic filtering nature and large SNDR make the tuner compatible with the very demanding ATSC A/74 standard. The chip's sophisticated digital back-end provides channel filtering and image rejection for the signal path, runs the RF and IF AGCs, and controls a variety of calibration schemes used to improve performance and robustness toward PVT variations. The chip has been designed in a scaled 90nm CMOS technology, requires a 1.8V analog supply and a 1.0V digital supply, and dissipates <450mW during normal operation and <10mW in standby mode. The BoM is limited to a single LNA bias inductor and a 40MHz crystal, thus minimizing the required footprint and cost.