Single-crystal Silicon Nanowires Research Articles

Ultrafine Filteration of Metal Catalysts Enables Fabrication of Silicon Nanowires with Diameter Approaching a Unit Cell Size

Advanced functionalities of silicon nanowires are size-dependent and downscaling of the nanostructure often leads to higher device performances. Single-crystal silicon nanowires with diameters approaching a single unit cell are fabricated using membrane-filtrated catalyst assisted chemical etching. Atomically filtrated gold is used as uniform pattern to direct anisotropic etching of dense silicon nanowire arrays. The size of the nanowires can be controlled by engineering the molecular weight of Poly(methyl methacrylate) used to fabricate the polymer globule membranes. The smallest silicon nanowires with 0.9 nm diameters exhibit direct, and wide band gap of 3.55 eV and establishes a new record. The experimentally obtained silicon nanowires in this size fill the valuable gap below the few-nanometer regime where to date only theoretical predictions have been available. This fabrication approach could provide facile access to atomic-scale silicon, which can bring further advancement to next generation nanodevices.

Optical Properties of Monocrystalline Silicon Nanowires

The paper presents the results of a study of the optical reflection and transmission spectra of a silicon single crystal p-Si (100) with silicon nanowires grown on both sides and porous silicon p-Si (100) on a single crystal substrate in the spectral range 0.2 ÷ 1.7 μm. The layers of nanowires had a thickness of 5.5 µm, 20 µm, 50 µm and a porosity of 60 %. The porous silicon layers had a thickness of 5 μm, 50 μm and a porosity of 45 %, 55 % and 65 %. The change in the energy band structure in single-crystal silicon nanowires and in a single-crystal matrix of porous silicon is shown.

Directed Self-Assembly of Block Copolymers for the Fabrication of Functional Devices.

Directed self-assembly of block copolymers is a bottom-up approach to nanofabrication that has attracted high interest in recent years due to its inherent simplicity, high throughput, low cost and potential for sub-10 nm resolution. In this paper, we review the main principles of directed self-assembly of block copolymers and give a brief overview of some of the most extended applications. We present a novel fabrication route based on the introduction of directed self-assembly of block copolymers as a patterning option for the fabrication of nanoelectromechanical systems. As a proof of concept, we demonstrate the fabrication of suspended silicon membranes clamped by dense arrays of single-crystal silicon nanowires of sub-10 nm diameter. Resulting devices can be further developed for building up high-sensitive mass sensors based on nanomechanical resonators.

What causes Poole-Frenkel transport in VLS grown silicon nanowires?

It is already established that Poole-Frenkel (PF) transport is the dominant method of current transport in gold-catalyzed, Vapor-Liquid-Solid (VLS) grown, intrinsic silicon nanowires. However, this is contrary to common knowledge in the field. PF transport is often used to model the current-voltage (IV) relationship of materials without long-range order. In this study, the physical nature of the coulomb traps responsible for PF transport in VLS grown silicon nanowires has been investigated. It has been found that, VLS grown, single crystal silicon nanowires have small regions (<25 nm2) of crystallographic misorientation throughout their volume. This, along with the twin boundaries found in the analysis, can periodically trap and detrap charge carriers traversing between the metal contacts on silicon nanowires. It is proposed that the omnipresence of these defects in the channel region to be the origin of PF transport in VLS grown silicon nanowires.

Plasmon‐Enhanced Silicon Nanowire Array‐Based Hybrid Heterojunction Solar Cells

In the last decade, freestanding, single crystal silicon nanowires (SiNWs) have attracted significant attention as a potential material for low‐cost optoelectronic devices. In this paper, we demonstrate how strong localized surface plasmon modes, induced using silver nanoparticles, can be used to achieve significant improvement in a simple hybrid organic–inorganic photovoltaic device between n‐type silicon nanowires and poly(3,4‐ethylenedioxythiophene):poly‐(styrenesulfonate) (PEDOT:PSS). At photon energies above plasmon resonance, metallic nanoparticle‐induced absorption leads to a dramatic reduction of the reflectivity and we report a significant improvement in both the short circuit current density (Jsc) and the open circuit voltage (Voc). This leads to an overall 52% increase in the power conversion efficiencies (PCEs) of the photovoltaic devices when decorating the SiNWs with silver nanoparticles prior to PEDOT:PSS deposition.

Hierarchical Multi-Diameter Single-Crystal Silicon Nanowires by Successive Wet Chemical Etching.

A simple and low cost top–down wet chemical etching method was developed to fabricate hierarchical multi-diameter well-ordered single-crystal silicon nanowires. The procedure starts with forming single diameter silicon nanowire arrays by using nanosphere lithography and metal-assisted chemical etching of single crystal silicon wafer, which is followed by anisotropic radial etching of the wires. Successive repetitions of these etching steps result in arrays of multi-diameter single crystal nanowires. This technique can allow engineering nanowires in a hierarchical three-dimensional geometry for the development of advanced nano devices.

25 nm Single-Crystal Silicon Nanowires Fabricated by Anisotropic Wet Etching.

We report a top-down method for fabricating ultra-high aspect ratio single-crystal silicon nanowires. The fabrication method is based on the standard photolithography technique and anisotropic wet etching of the single-crystal silicon in KOH solution. SiO₂ mask nanolines used for patterning single-crystal silicon nanowires are formed by the undercut etching of thin SiO₂ layer in buffered hydrofluoric solution. The minimum width of the SiO₂ mask nanolines are 50 nm. The length of SiO₂ mask nanolines is 2 cm. The single-crystal silicon nanowires have been successfully transferred from the SiO₂ mask nanolines by KOH anisotropic wet-chemical etching. The minimum width of the silicon nanowire has obtained to be 25 nm. The fabricated single-crystal silicon nanowires have trapezoidal and triangular cross sections, which are useful for applications in nanoelectronic and nanophotonic elements.

Tensile fracture of integrated single-crystal silicon nanowire using MEMS electrostatic testing device

Tensile testing of single-crystal silicon (SCS) nanowire integrated into electrostatic micro electro mechanical system (MEMS) device was conducted. The nanowire was fabricated using batch process for future integration of nanowires to MEMS sensors or actuators. The tensile specimen of SCS nanowire has a circular cross section of 100 to 200 nm in diameter, 5 μm long. The diameter was controlled by oxidizing 800-nm square cross-section wires fabricated using electron beam lithography. The oxidizing thinning process also reduced the surface roughness. On-chip tensile testing using an electrostatic actuator and sensor was conducted for the specimen of 190 nm in cross-section size. The tensile strength of the wire was 2.6 GPa. The strength and fracture properties were discussed by comparing with a silicon nanowire fabricated using two-step Bosch process to examine the difference in surface finishing.

Fabrication of single-crystal silicon nanowires based on surface wet adhesion

In this paper, we present a top–down fabrication method of single-crystal silicon nanowires. The method employs the popular photolithography technique and etching-rate dependent on the crystal orientation of single-crystal silicon in KOH solution. Using surface wet adhesion and reduced silicon dioxide etching, nanoscale SiO2 mask line patterns with width from 45nm to 200nm and length up to 120µm are successfully patterned. The interspace between nanoscale SiO2 mask lines is 750nm, which is narrower than the 1.2µm feature resolution of obtainable photolithography process. A mechanism for explaining the creation of nanoscale SiO2 mask lines based on surface wet adhesion due to the capillary force is suggested and discussed. The single-crystal silicon nanowires have been successfully fabricated by transferring the nanoscale SiO2 mask line patterns into the top silicon layer of SOI wafer by KOH anisotropic wet-chemical etching.

Formation of Single Crystal Si-Nanowire by Electric Field Self-Redistribution Effect in Anodic Oxidation for Multilayer Array Application

Single crystal silicon nanowire was formed successfully by electric field self-redistribution effect in anodic oxidation (ANO) with room temperature process. By using the ANO process with large electric field and long oxidation time, nanowires with a diameter of 9 nm can be achieved in this study. The silicon nanowire with tunable diameter in double layer array was automatically formed due to the self-ending oxidation blocking caused by the self-redistribution nature of electric field. The E-beam lithography with different photoresist widths from 60 to 90 nm was designed for observing the formation of nanowire. It can be observed that the convex profile of silicon shows larger electric field than concave profile in the ANO process and therefore induces thicker oxide. The single crystal Si-nanowire array by the ANO process is potential for the complementary metal–oxide–semiconductor devices application in the next generation.

Subeutectic growth of single-crystal silicon nanowires grown on and wrapped with graphene nanosheets: high-performance anode material for lithium-ion battery.

A novel one-pot synthesis for the subeutectic growth of (111) oriented Si nanowires on an in situ formed nickel nanoparticle catalyst prepared from an inexpensive nickel nitrate precursor is developed. Additionally, anchoring the nickel nanoparticles to a simultaneously reduced graphene oxide support created synergy between the individual components of the c-SiNW-G composite, which greatly improved the reversible charge capacity and it is retention at high current density when applied as an anode for a Li-ion battery. The c-SiNW-G electrodes for Li-ion battery achieved excellent high-rate performance, producing a stable reversible capacity of 550 mAh g(-1) after 100 cycles at 6.8 A g(-1) (78% of that at 0.1 A g(-1)). Thus, with further development this process creates an important building block for a new wave of low-cost silicon nanowire materials and a promising avenue for high rate Li-ion batteries.

Study of silicon crystal surface formation based on molecular dynamics simulation results

The equilibrium shape of 〈110〉-oriented single crystal silicon nanowire, 8nm in cross-section, was found from molecular dynamics simulations using LAMMPS molecular dynamics package. The calculated shape agrees well to the shape predicted from experimental observations of nanocavities in silicon crystals. By parametrization of the shape and scaling to a known value of {111} surface energy, Wulff form for solid-vapor interface was obtained. The Wulff form for solid–liquid interface was constructed using the same model of the shape as for the solid–vapor interface. The parameters describing solid–liquid interface shape were found using values of surface energies in low-index directions known from published molecular dynamics simulations. Using an experimental value of the liquid–vapor interface energy for silicon and graphical solution of Herring's equation, we constructed angular diagram showing relative equilibrium orientation of solid–liquid, liquid–vapor and solid–vapor interfaces at the triple phase line. The diagram gives quantitative predictions about growth angles for different growth directions and formation of facets on the solid–liquid and solid–vapor interfaces. The diagram can be used to describe growth ridges appearing on the crystal surface grown from a melt. Qualitative comparison to the ridges of a Float zone silicon crystal cone is given.

Significant reduction of thermal conductivity in silicon nanowire arrays

Vertically aligned single-crystal silicon nanowire arrays (SiNWs) with various lengths, surface roughnesses and porosities were fabricated with the metal-assisted chemical etching method. Using the laser flash technique and differential scanning calorimetry, we characterized the thermal conductivities of bulk SiNWs/Si/SiNWs sandwich-structured composites (SSCs) at room temperature (300 K). The results demonstrate that the thermal conductivities of SSCs notably decrease with increases in the length, surface roughness and porosity of SiNWs. Furthermore, based on the series thermal-resistance model, we calculated the thermal conductivity of porous SiNWs to be as low as 1.68 W m−1 K−1 at 300 K. Considering the remarkable phonon scattering from the diameter, surface roughness and porosity of SiNWs, leading to a significant reduction of the thermal conductivity, SSCs and SiNWs could be applied to high-performance thermoelectric devices.

Silicon nanowires with controlled sidewall profile and roughness fabricated by thin-film dewetting and metal-assisted chemical etching

This paper presents a non-lithographic approach to generate wafer-scale single crystal silicon nanowires (SiNWs) with controlled sidewall profile and surface morphology. The approach begins with silver (Ag) thin-film thermal dewetting, gold (Au) deposition and lift-off to generate a large-scale Au mesh on Si substrates. This is followed by metal-assisted chemical etching (MacEtch), where the Au mesh serves as a catalyst to produce arrays of smooth Si nanowires with tunable taper up to 13°. The mean diameter of the thus fabricated SiNWs can be controlled to range from 62 to 300 nm with standard deviations as small as 13.6 nm, and the areal coverage of the wire arrays can be up to 46%. Control of the mean wire diameter is achieved by controlling the pore diameter of the metallic mesh which is, in turn, controlled by adjusting the initial thin-film thickness and deposition rate. To control the wire surface morphology, a post-fabrication roughening step is added to the approach. This step uses Au nanoparticles and slow-rate MacEtch to produce rms surface roughness up to 3.6 nm.

Optical properties and quantum confinement in ultrafine single crystal silicon nanowires synthesized by thermal evaporation without catalyst

Ultrafine single crystal silicon nanowires (SiNWs) were grown along the direction by thermal evaporation without catalyst, and were studied by electron microscopy and optical spectroscopy. Simulation of the first-order Raman scattering spectrum of the wires indicates that the Raman shift and asymmetric broadening line shape are due to phonon confinement and a narrow diameter distribution of the SiNWs, and confirms that the mean diameter of the wires is 2 nm, which is smaller than the excitonic Bohr radius of Si. Further analysis shows that the unique intense purple photoluminescence (PL) peak and blue-shift of absorption spectrum of the wires result both from the increase of the energy band gap due to quantum confinement of the carriers, and from the confinement of excitons in the ultrafine SiNWs, suggesting potential applications of the wires in optical and optoelectronic nanoscale devices.

Large initial compressive stress in top-down fabricated silicon nanowires evidenced by static buckling

Single crystal silicon nanowires with a width down to 25 nm and a length-to-width (L/w) aspect ratio up to 177 were fabricated by surface micromachining of thin SOI wafers. It is demonstrated that these top-down fabricated clamped-clamped nanowires are laterally buckled when L/w is larger than about 44. This is attributed to an unexpected high compressive residual pre-stress estimated to be in the −270 to −335 MPa range from a simple nonlinear post-buckling model. The origin of this stress is investigated by considering several axial stress generation mechanisms in the silicon nanowires such as thermomechanical stresses, surface layers and deformation stresses of dies induced by patterning or die attachment. It is shown that none of these mechanisms can generate the observed initial compressive stress and high temperature steps during SOI wafers fabrication and/or thinning are likely to be the main cause of high compressive stress generation. Possible occurrence of a large stress in top-down fabricated Si nanowires is often ignored and must be considered in future works notably for electrical and thermal transport investigations.

Fabrication of Three-Dimensional MIS Nano-Capacitor Based on Nanoimprinted Single Crystal Silicon Nanowire Arrays

We report fabrication of single crystalline silicon nanowire based-three-dimensional MIS nano-capacitors for potential analog and mixed signal applications. The array of nanowires is patterned by Step and Flash Imprint Lithography (S-FIL). Deep silicon etching (DSE) is used to form the nanowires with high aspect ratio, increase the electrode area and thus significantly enhance the capacitance. High-! dielectric is deposited by highly conformal atomic layer deposition (ALD) Al2O3 over the Si nanowires, and sputtered metal TaN serves as the electrode. Electrical measurements of fabricated capacitors show the expected increase of capacitance with greater nanowire height and decreasing dielectric thickness, consistent with calculations. Leakage current and time-dependent dielectric breakdown (TDDB) are also measured and compared with planar MIS capacitors. In view of greater interest in 3D transistor architectures, such as FinFETs, 3D high density MIS capacitors offer an attractive device technology for analog and mixed signal applications.

Top-down fabrication of single crystal silicon nanowire using optical lithography

A method for fabricating single crystal silicon nanowires is presented using top-down optical lithography and anisotropic etching. Wire diameters as small as 10 nm are demonstrated using silicon on insulator substrates. Structural characterization confirms that wires are straight, have a triangular cross section and are without breakages over lengths of tens of microns. Electrical characterization indicates bulk like mobility values, not strongly influenced by surface scattering or quantum confinement. Processing is compatible with conventional silicon technology having much larger critical dimensions. Integrating such nanowires with a mature CMOS technology offers an inexpensive route to their exploitation as sensors.

Compression of Nanowires Using a Flat Indenter: Diametrical Elasticity Measurement

A new experimental approach for the characterization of the diametrical elastic modulus of individual nanowires is proposed by implementing a micro/nanoscale diametrical compression test geometry, using a flat punch indenter. A 250 nm diameter single crystal silicon nanowire is compressed inside of a scanning electron microscope. Since silicon is highly anisotropic, the wire crystal orientation in the compression axis is determined by electron backscatter diffraction. In order to analyze the load-displacement compression data, a two-dimensional analytical closed-form solution based on a classical contact model is proposed. The results of the analytical model are compared with those of finite element simulations and to the experimental diametrical compression results and show good agreement.

Low-Cost, Large-Scale, and Facile Production of Si Nanowires Exhibiting Enhanced Third-Order Optical Nonlinearity

A facile method for the low-cost and large-scale production of silicon nanowires has been developed. Silicon powders were subjected to sequential metal plating and metal-assisted chemical etching, resulting in well-defined silicon nanowires. The morphology and structure of the silicon nanowires were investigated, revealing that single-crystal silicon nanowires with average diameters of 79 ± 35 nm and length more than 10 μm can be fabricated. The silicon nanowires show excellent third-order nonlinear optical properties, with a third-order susceptibility much larger than that of bulk silicon, porous silicon, and silicon nanocrystals embedded in SiO(2).