Single Phase Clock Research Articles

VLFF — A very low-power flip-flop with only two clock transistors

Flip-flops (FFs) are an essential component of digital circuits, yet they use a lot of power and energy. This paper introduces the VLFF, an extremely low-power flip-flop that operates with just two single-phase clock transistors. The extracted simulation results show that VLFF is the most power-efficient FF amongst all examined FFs for the data activity (DA) range of 0% to 45%. Test-chip measurement results for the test-chip designed in TSMC CMOS 65 nm gp PDK demonstrate that at VDD = 1 V, power consumption is reduced by 63% and 16% with 12.5% DA, and 52% and 6% with 25% DA in comparison to TGFF and 18TSPC, respectively.

A power-efficient, single-phase, contention-free flip-flop with only three clock transistors

Flip-flop research in recent years has been motivated by power- and/or energy-efficient designs. Flip-flop power is based on data activity (DA), which in many applications ranges from 5 to 15%. In such cases, a substantial amount of clock power and energy is wasted. In this paper, a power-efficient, contention-free flip-flop with only three single-phase clock transistors is proposed, which has low-power consumption and eliminates unnecessary internal transitions in the circuit. This flip-flop is referred as 3CTSPC. Test-chip measurement results show that at VDD = 1 V, CK = 25 MHz, and DA = 12.5%, 3CTSPC is 11% and 58% more power-efficient than 18TSPC and TGFF, respectively.

Design and Analysis of Low-Power and Area-Efficient Master-Slave Flip-Flop

In this paper, a novel master-slave flip-flop is designed that incorporates 15 transistors and a single-phase clock, employing topological and adaptive coupling methods. The proposed flip-flop circuit (PFC) is more efficient than other logic-structured flip-flops. PFC is designed using a 45 nm Complementary Metal Oxide Semiconductor (CMOS) technology node. Notably, the PFC exhibits an impressive 34.18%, 42.92%, 39.71%, 44.39%, and 46.91% improvement in average power consumption compared to the adaptive data track flip-flop (ADTFF), Hybrid Flip-Flop (HFF),18-transistor single-phase clocked (18TSPC), Logic Structured Reduction Flip-Flop (LSRFF), and Topologically compressed flip-flop (TCFF). It also improved the C to Q delay, power delay product (PDP). Monte Carlo simulations of average power and C to Q delay have been performed for 1000 samples. By reducing the number of PMOS transistors, the total area of the PFC is minimized. PFC operates effectively within a clock frequency range of up to 1 GHz.

A low-jitter and low-phase noise switched-loop filter PLL using fast phase-error correction and dual-edge phase comparison technique

This paper presents a low-jitter and low-phase noise type-II charge pump and switched-loop filter-based (SLF) phase-locked loop (PLL) with a fast phase error correction technique (FPEC) and a newly proposed dual-edge phase comparator (DEPC). To improve the phase noise, the bandwidth of the proposed PLL is extended to fREF/5 using the proposed DEPC. It consists of four D flip-flops in true single-phase clock (TSPC) logic, four current-mode logic-based inverters, and two logic OR gates. Unlike conventional DEPCs, the proposed DEPC has a small reset pulse width duration and negligible blind zone, and due to this, it can perform at higher frequencies along with an increased phase detection range. The proposed architecture is implemented for a 2.4 GHz output frequency that embodies DEPC and SLF using the FPEC technique in an 180-nm Semi-Conductor Laboratory (SCL) CMOS process. The proposed DEPC can work up to a maximum of 3.45 GHz frequency with 145 ps of reset delay. The proposed PLL accomplishes the 40 MHz bandwidth with a 200 MHz reference clock. The simulated rms jitter integrated from 10 kHz to 100 MHz and the phase noise of the output signal at an offset of 1 MHz are 860 fs and −122 dBc/Hz respectively. The proposed architecture occupies an area of 0.032 mm2 and consumes 8.2 mW from 1.8 V power supply.

An Extended Range Divider Technique for Multi-Band PLL

This paper presents a multiplexer-based extended range multi-modulus divider (ER-MMD) technique for multi-band phase locked loop (PLL). The architecture maintains a modular structure by using conventional 2/3 divider cells and a multiplexer without adding any extra logic circuitry. The area and power overhead is minimal. The 2/3 divider cells are designed using true single phase clock (TSPC) logic for ER-MMD to operate in the sub-10 GHz range. A division range of 2 to 511 is achieved using this logic. The ER-MMD operates at a maximum frequency of 6 GHz with a worst-case current of 625 μA when powered with a 1 V supply. A dual voltage controlled oscillator (VCO), L5/S band PLL for Indian Regional Navigation Satellite System (IRNSS) application is designed, which incorporates an ER-MMD based on the proposed approach as a proof of concept. This technique achieves the best power efficiency of 12 GHz/mW, among the state-of-the-art ER-MMD designs.

Design of a multi-modulus divider with a wide frequency dividing range and low power consumption

A method of moduli expansion was presented to address the issue of wrongly altering the divider ratio at the boundary of the modulus expansion when multi-mode dividers (MMD) were utilized in fractional-N phase locked loops (PLLs). The multi-mode frequency divider was designed as the cascade of the 2/3 frequency dividers with an RS control terminal. Compared to traditional methods, only one OR gate is required for each modulus expansion, reducing the chip area. The 2/3 divider was designed using a True Single-Phase Clocked (TSPC) D-trigger structure, and each D-trigger uses a logic control technique with clearing and setting the number. An eight-stage multi-mode frequency divider with modulus expansion was developed using SMIC 55 nm CMOS technology. The simulation results demonstrated the large frequency divider range of the multi-mode frequency divider and its ability to carry out consistent switching operations over the 8–511 frequency divider range. The power consumption is 66.04W at a supply voltage of 1V, an input frequency of 2GHz, and an output frequency of 250MHz.

TSPC-AVLS Based Low-Power 16/17 Dual Modulus Pre-Scaler Design

Dual modulus pre-scalers (DMPS) are programmable counters used in phase-locked loops (PLL). The dual modulus division capability improves the circuit functionality and can be used as a divider of N/N + 1 cycles, which can be controlled through a master input. This paper proposes power and area efficient divide-by-16/17 DMPS designs, which incorporate true single-phase clocking (TSPC) based D flip-flops, which consume less power with minimal area. Power reduction is achieved by integrating adaptive voltage level-source (AVLS) circuit to DMPS. The proposed-I divide-by-16/17 DMPS has been implemented by using TSPC based D flip-flops incorporating the AVLS technique. The proposed DMPS consumes 146.6 µW (34%) less power when compared to the reference architecture, in divide-by-16 mode. Further optimization of the pre-scaler design is done by using a minimum number of transistors, involving pushing the logic (AND) into the first stage of TSPC based D flip-flops which results in an area as well as power efficient design. The proposed-II circuit is realized by using optimized TSPC based D flip-flops, along with incorporation of the AVLS technique, resulting in a power efficient design. For instance, in divide-by-16 mode of operation, a 100 µW (21%) reduction in the total power is observed when a DMPS circuit is realized in CMOS 180 nm technology. Also, when the proposed DMPSs are realized in CMOS 45 nm technology, the same trend of power reduction is observed, which are analyzed at an operating frequency of 1 GHz. The circuits are realized in Cadence Virtuoso and simulated in Spectre.

AVLS-based 32/33 Pre-scaler for frequency dividers

Pre-scalers are widely used in phase-locked loops (PLL) which are vital components in communication systems. The Dual Modulus Pre-Scaler (DMPS) has dual division capability, to divide the clock by N/N+1 cycles, which can be controlled by the designer based on the control circuitry. Pre-scaler circuits are used to divide the received signal to obtain integer multiples of the received signal. This paper proposes a power efficient 32/33 pre-scaler for high-frequency operation. DMPS is composed of a series of D Flip-flops (D-FF) and logic gates along with feedback connection between the different stages. Clock skew is of major concern in the D-FFs, which can be reduced by realizing D-FFs using true single-phase clock (TSPC) logic. Furthermore, the incorporation of an Adaptive Voltage Level Source (AVLS) circuit decreases the power consumption of the circuits. By integrating the AVLS circuit to divide-by-32/33 DMPS, low power consumption is achieved. At different operating frequencies, both divide-by-32 and -33 modes of the proposed 32/33 DMPS with AVLS were analyzed. In comparison to the reference pre-scaler circuit, the proposed pre-scaler consumes 35.65% less power at 1GHz. CMOS 180nm technology in Cadence Virtuoso is used to realize circuits and Cadence Spectre is used to simulate circuits.

Metastability Error Correction for True Single-Phase Clock DFF With Applications in Vernier TDC

This brief investigates the characteristics and impact of the metastabity of true single-phase clock DFFs used for catch detection in Vernier TDCs, and proposes a metastability error correction technique that automatically eliminates the metastability-induced errors of Vernier TDCs. The effectiveness of the proposed technique is assessed using an 8-stage Vernier TDC with metastability error correction catch-detect DFFs. The TDC is designed in a TSMC 130 nm 1.2 V CMOS technology and analyzed using Spectre from Cadence Design Systems with BSIM3.3 device models. Simulation results demonstrate the proposed technique completely eliminates metastability-induced errors of Vernier TDCs at the cost of an additional power, area, and delay.

A low power high speed single phase clock level restoring 16T master-slave flip-flop

PurposeA low power flip-flop circuit is designed for energy-efficient devices. Digital sequential circuits are in huge demand because every processor has most of the parts of digital circuit. The sequential circuits consist of a basic data storing element, a latch is used to store single bit data. The flip-flop takes a sufficient portion of the total chip area and overall power consumption as well. This study aims to the low power energy-efficient applications like laptops, mobile phones and palmtops.Design/methodology/approachThis paper proposes a new type of flip-flop that consists of the only 16 transistors with a single-phase clock. The flip-flop has two blocks, master and slave latch. In this design, the authors have focused on only master latch, which includes a level restoring circuit. It is used to help the master latch in data retention process. The latch circuit has two inverters in back-to-back arrangement. The proposed flip-flop is implemented on 65 nm complementary metal oxide semiconductor technology using Cadence Virtuoso environment and compared with other reported flip-flops.FindingsThe proposed flip-flop architecture outperformed the peak percentage, i.e. 79.25% as compared to transmission gate flip-flop and a minimum of 20.02% compared to 18 T true single phase clocking (TSPC) improvement in terms of power. It also improved C to Q delay and power delay product. In addition, by reducing the number of transistors the total area of the proposed flip-flop is reduced by a minimum of 13.76% with respect to 18TSPC and existing flip-flop. For reliability checking the Monte Carlo simulation is performed for thousand samples and it is compared with the recently reported 18TSPC flip-flop.Originality/valueThis work is tested by using a test circuit with a load capacitor of 0.2 fF. The proposed work uses a new topology to work as master-slave. Power consumption of this technique is very less and it is best suitable for low power applications. This circuit is working properly up to 2 GHz frequency.

True Single Phase Clock based UP-DOWN Counter using GDI Cell for Low Power Applications

True Single Phase Clock based UP-DOWN Counter using GDI Cell for Low Power Applications

A Novel Radiation-Hardened CCDM-TSPC Compared with Seven Well-Known RHBD Flip-Flops in 180 nm CMOS Process

Numerous radiation-hardened-by-design (RHBD) flip-flops have been developed to increase the dependability of digital chips for space applications over the past two decades. In this paper, the radiation immunity and performance of seven well-known RHBD flip-flops are discussed. A novel cross-connected dual modular redundant true single-phase clock (TSPC) D flip-flop (CCDM-TSPC) is proposed. The presented CCDM-TSPC replaces the typical master-slave D flip-flop (MS-DFF) with the fundamental TSPC structure to shorten the circuit’s propagation time. All sensitive points in the circuit are radiation-hardened by using means of cross-connection. The simulation results of the SPECTRE tool show that CCDM-TSPC is completely immune to single-event upsets (SEUs). CCDM-TSPC reduces the C-Q delay by 75% and the layout area by 85% compared with the traditional triple modular redundancy D flip-flop (TMR-DFF).

Comparative Analysis of Single-Phase-Clocked Low Power Flip-Flops with Transmission-Gate Flip-Flop

Flip-flops are fundamental building block in designing the digital circuits. They contribute significant amount of power consumption in the digital systems. In the modern era of VLSI design, power consumption has become crucial factor. As the technology is scaled down below 65nm, leakage power contributes significantly to overall power consumption of digital circuits. Since, Flip-flop is a fundamental building block in designing digital systems, reducing the power consumption of Flip-flop is required to achieve low power consumption of digital systems. Recently single-phase clocking technique has been employed in designing FFs to achieve low power consumption. This technique reduces excess loading on the clock signal. In this article performance of recent single-phase clocked FFs is compared with the conventional transmission-gate Flip-flop. Also, drawbacks of these FFs are discussed. For the comparison of performance of single-phase-clocked FFs with conventional transmission-gate FF, all the simulations are performed at 45-nm predictive technology on Tanner EDA tool.

TSPC-HNTL: True Single Phase Clock technique for High speed, Noise Tolerance, and Low power

TSPC-HNTL: True Single Phase Clock technique for High speed, Noise Tolerance, and Low power

A 1.24-pJ/b 112-Gb/s (870 Gb/s/Mm) Transceiver for In-Package Links in 7-nm FinFET

This article describes the design of a 1.24-pJ/b 112-Gb/s PAM4 transceiver test chip in 7-nm FinFET for in-package die-to-die communication. The receiver supports 0–1.2-V input common mode and utilizes a single-stage active inductor-based CMOS continuous-time linear equalizer (CTLE) with 12 data slicers and two error slicers. The quad-rate voltage-mode transmitter implements delay-based sub-UI two-tap FFE and digital I/Q and DCC clock calibration. A single-phase clock from a wideband <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">LC</i> phase-locked loop (PLL) is distributed to eight transceiver channels. In each channel, an injection-locked oscillator (ILO) generates eight-phase clocks that feed an 8-bit CMOS phase interpolator (PI). The transceiver achieves < 1e <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">−12</sup> bit error rate (BER) over 30-mm channel at 106.25 Gb/s and over 20-mm channel at 112 Gb/s.

A 0.35-mW 70-GHz Self-Resonant E-TSPC Frequency Divider With Backgate Adjustment

This research work presents the analysis, design, and characterization of a concept for an mm-wave divide-by-4 frequency divider utilizing an extended true single-phase clock (E-TSPC) and a TSPC divide-by-2 stage. The divider operates from 16 to 70 GHz from a 0.8-V supply with the highest power consumption of 0.35 mW. Operating frequencies up to 53 GHz were reached with a supply voltage of only 0.5 V at 0.12-mW power consumption. The self-resonance frequency of the circuit is adjustable through backgate biasing from 40 up to 70 GHz at 0.9-V supply, allowing a reduction in the required input power in this frequency range. Locking ranges up to 114% have been measured by changing only the backgate voltage. The circuit design is illustrated in detail and supported with original analysis and an explicit expression to calculate the self-oscillation frequency of the E-TSPC divider. The presented circuit was fabricated on a 22-nm fully depleted silicon-on-isolator complementary metal–oxide–semiconductor (CMOS) technology and occupies an active area of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$3.4 ~\mu \text{m}^{2}$ </tex-math></inline-formula> . The circuit requires the lowest power consumption and area among state-of-the-art RF frequency dividers, while it demonstrates the second widest adjustable operating frequency range and the second highest self-resonance frequency for CMOS D-flip-flop frequency dividers.

Improved Metastability of True Single-Phase Clock D-Flipflops With Applications in Vernier Time-to-Digital Converters

This paper investigates the metastability of true single-phase clock (TSPC) D flip flops (DFFs) and its impact on the resolution of Vernier time-to-digital converters (TDCs). The mechanisms of the metastability of TSPC DFFs are investigated and the analytical expressions of setup time and hold time are obtained. A shunt capacitor technique capable of reducing setup time and hold time to zero with no power and delay penalty is proposed. The impact of PVT (process, voltage, temperature) on the effectiveness of the proposed technique is quantified using simulation. Vernier TDCs, both right-shifting and left-shifting, with untuned and tuned DFFs are designed in TSMC 130 nm 1.2 V CMOS technology and analyzed using Spectre with BSIM3V3 device models. Simulation results demonstrate TDCs with tuned DFFs enjoy zero conversion error while the right-shifting and left-shifting TDCs with untuned DFFs have 1-bit and 5-bit conversion errors or 11% and 56% error rates, respectively.

Power optimization in TSPC D flip-flop based 4-bit counter

In the present communication, the basic D flip flop has been considered with TSPC (True Single Phase Clock) logic for designing a novel 4-bit counter on 45 and 32nm technology. Here, it was with average power of 309 μWatts and 166.8 μWatts, which is very high on the respective technologies. The challenge is to reduce the average power and off state leakage power. To consider the challenge, two different techniques have been considered for power saving as, sleeping transistors and technique, modified TSPC D flip-flop (modified version In comparative study of simulations, it is observed that employing modified version of TSPC D flip-flop shows the most optimum results in terms of propagation delays and average power. Average power has been obtained as 260.3 μWatts which is 15.76% less than base counter on 45nm technology, and 133.2 μWatts which is 20.14 % less on 32nm technology. Moreover, Transistor sizing has also been used for separate analysis in which case the average power consumption has been found most minimum in 6/4 aspect ratio as 196.6 μWatts and 70.31 μWatts in both technologies respectively, among 6/4, 5/3 and 4/2 ratios.

Leakage power optimization using sleeping approaches in TSPC D flip-flop

In this paper, the basic D flip-flop has been considered with TSPC (True Single-Phase Clock) logic. Here, the leakage power of 1031 pW fell to the power for the operation of the memory elements, which is a lot compared to other triggers. The challenge is to reduce the optimal power off to conserve idle power. To solve this problem, three different powersaving techniques were considered, such as Technique 1: sleeping transistors, Technique 2: sleepy stack, and Technique 3: sleepy keeper. In a comparative study, it was observed that Technique 1 is the most optimal method for delays (falling and rising) and off-state leakage power compared to the other methods considered. The off-state leakage power was 1.753 pW, which is 93.07% and 76.90% less than by Techniques 2 and 3, respectively.

An efficient 70 GHz divide‐by‐4 CMOS frequency divider employing low threshold devices

The idea to use a lower threshold, but slightly slower transistor over the fastest transistor type for large-signal circuits is presented with experimental verification for a compact divide-by-4 true single phase clock (TSPC) frequency divider. The use of the lowest threshold PMOS devices resulted in self-resonance frequencies of 41.7, 56, and 60 GHz at supply voltages of 0.5, 0.8 and 0.9 V, respectively. Compared to a divider of the same architecture in the same technology, but with higher threshold voltage devices, this corresponds to improvements of 67%, 33% and 27%, respectively. Power consumptions of 26 and 355 μW were measured for a 20 GHz and a 70 GHz input signal for supply voltages of 0.5 and 0.9 V, respectively. The best knowledge of the authors, these results are the best reported to date for TSPC divider architecture, and they compete with state of the art for inductorless current-mode logic dividers.