TSPC-AVLS Based Low-Power 16/17 Dual Modulus Pre-Scaler Design

Abstract

Dual modulus pre-scalers (DMPS) are programmable counters used in phase-locked loops (PLL). The dual modulus division capability improves the circuit functionality and can be used as a divider of N/N + 1 cycles, which can be controlled through a master input. This paper proposes power and area efficient divide-by-16/17 DMPS designs, which incorporate true single-phase clocking (TSPC) based D flip-flops, which consume less power with minimal area. Power reduction is achieved by integrating adaptive voltage level-source (AVLS) circuit to DMPS. The proposed-I divide-by-16/17 DMPS has been implemented by using TSPC based D flip-flops incorporating the AVLS technique. The proposed DMPS consumes 146.6 µW (34%) less power when compared to the reference architecture, in divide-by-16 mode. Further optimization of the pre-scaler design is done by using a minimum number of transistors, involving pushing the logic (AND) into the first stage of TSPC based D flip-flops which results in an area as well as power efficient design. The proposed-II circuit is realized by using optimized TSPC based D flip-flops, along with incorporation of the AVLS technique, resulting in a power efficient design. For instance, in divide-by-16 mode of operation, a 100 µW (21%) reduction in the total power is observed when a DMPS circuit is realized in CMOS 180 nm technology. Also, when the proposed DMPSs are realized in CMOS 45 nm technology, the same trend of power reduction is observed, which are analyzed at an operating frequency of 1 GHz. The circuits are realized in Cadence Virtuoso and simulated in Spectre.