Single-chip System Research Articles

Single-chip microcomputer system for auricular diagnosis and treatment

Single-chip microcomputer system for auricular diagnosis and treatment

A single-chip public key encryption subsystem

A single-chip system capable of encryption using the Rivest, Shamir, and Adleman algorithm at rates significantly higher than other implementations is reported. The chip uses a self-timed methodology and has been implemented in a 2 mu m technology. The chip is a complete system and includes registers for the storage of keys for duplex operation. It is provided with a standard interface to a number of common microprocessors.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A 16-bit multiflow concurrent processor for VTR control

A processor architecture is presented that uses a multiconcurrent processing loop consisting of multiple central processing units and processing instructions in a master-slave type relationship. Using this architecture, a 16-bit CMOS concurrent processor and software were developed for controlling a videotape recorder (VTR). This single-chip system provides concurrent actuation of various motors and system control of the VTR. The processor IC is 5.6 mm by 6.8 mm, containing about 160000 digital and 1900 analog elements. It is configured as a 76-pin DIP (dual in-line package) with a typical power consumption of 120 mW.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Design of Single-Chip Microprocessor-Based Controller for Current Source Inverter-Fed Induction Motor Drive

The single-chip microcomputer MC68701-based inverter gating system is proposed in this paper. The three-phase converter and inverter gatings occur independently and the current source inverter-fed induction motor controller with voltage feedback is also implemented in a single microprocessor. The accuracy of gating is about 1 deg in converter delay angle at line frequency 60 Hz and 0.19 percent in inverter frequency at output frequency 60 Hz. The proposed system is applied to 100-hp induction motor drive.

Flexible speech synthesis using a single chip system

Speech system design has been limited in the past by power consumption considerations, data format versus system interface trade‐offs, and general system complexity in multi‐chip systems. A CMOS speech synthesizer/ROM/processor, recently designed, solves these problems. The device consists of an 8‐bit speech processor, 8K bytes of ROM, LPC‐10 lattice filter, and a pulse width modulating D/A. The general purpose data I/O port is designed consistent with TTL interface requirements and may be directly interfaced to four‐ and eight‐bit microprocessors and also used directly with a key matrix. Since the chip has an onboard ROM, it provides a single chip system for many speech applications. The programmability of the speech processor in the device makes it sufficiently flexible to process various speech data formats to achieve specific synthesis requirements.

A CCD color signal separation IC for single-chip color imagers

A CCD color signal separation IC for solid-state imagers with color filter arrays is described. The device simplifies peripheral circuitry and enhances picture qualities such as resolution, color fidelity, and stability for single-chip color imaging systems, by incorporating CCD delay lines, sample-and-hold circuits, and dual clamp circuit. Also described is a new geometry color filter array which is required by the separation IC. Color image corresponding to horizontal resolution of 340 TV lines with no erroneous color has been obtained from the device when used with a 580 × 475 element CCD imager.

A CCD color signal separation IC for single-chip color imagers

A CCD color signal separation IC for solid-state imagers with color filter arrays is described. The device simplifies peripheral circuitry and enhances picture qualities such as resolution, color fidelity, and stability for single-chip color imaging systems by incorporating CCD delay lines, sample-and-hold circuits, and dual clamp circuit. Also described is a color filter array utilizing Bayer geometry, which is used in the separation IC. Color images corresponding to a horizontal resolution of 340 TV lines with no erroneous color have been obtained from the device when used with a 580/spl times/475 element CCD imager.

Molybdenum gate MOS applied to an AM/FM digital frequency synthesizer

An n-channel molybdenum self-aligned gate MOS technology has been developed and applied to an AM/FM digital frequency synthesizer. A high-frequency programmable divider operating at 180 MHz has been achieved by the use of molybdenum, low parasitic capacitance structures and zero-threshold MOS transistors, while maintaining conventional design rules. Molybdenum gate MOS has enabled the realization of a single-chip system, which consists of a directly programmable divider for the AM/FM local oscillators, a reference counter, a phase comparator, a circuit for dial tuning, and memories for storing the frequencies for 16 stations. A differential comparator has been fabricated on the LSI chip to simplify digital tuning in the receiver.