Abstract
A processor architecture is presented that uses a multiconcurrent processing loop consisting of multiple central processing units and processing instructions in a master-slave type relationship. Using this architecture, a 16-bit CMOS concurrent processor and software were developed for controlling a videotape recorder (VTR). This single-chip system provides concurrent actuation of various motors and system control of the VTR. The processor IC is 5.6 mm by 6.8 mm, containing about 160000 digital and 1900 analog elements. It is configured as a 76-pin DIP (dual in-line package) with a typical power consumption of 120 mW.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
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