Circuit Simulation Research Articles

On the realization of an amplifier‐tuned low/high frequency family of oscillators

SummaryWe propose a family of equal‐R equal‐C dual amplifier oscillators with gain‐tunable start‐up condition and oscillation frequency. In particular, while one of the amplifiers can be used to satisfy the oscillator start‐up condition, the second amplifier can be used to tune the oscillation frequency. In this regard, it is observed that the oscillation frequency can be made very low or very high independent of the RC time constant of the circuit by properly choosing the amplifier gain and the circuit topology. In one possible topology, the oscillation frequency is directly proportional to the tuning amplifier gain, while in a second topology, it is inversely proportional to this gain. Both topologies generate two outputs which also have a gain‐tunable leading or lagging phase shift. Circuit simulations and experimental results are presented to verify the theory in addition to a non‐conventional application in chaos generation.

Tau-Cell-Based Analog Silicon Retina With Spatio- Temporal Filtering and Contrast Gain Control.

Developing precise artificial retinas is crucial because they hold the potential to restore vision, improve visual prosthetics, and enhance computer vision systems. Emulating the luminance and contrast adaption features of the retina is essential to improve visual perception and efficiency to provide an environment realistic representation to the user. In this article, we introduce an artificial retina model that leverages its potent adaptation to luminance and contrast to enhance vision sensing and information processing. The model has the ability to achieve the realization of both tonic and phasic cells in the simplest manner. We have implemented the retina model using 0.18 μm process technology and validated the accuracy of the hardware implementation through circuit simulation that closely matches the software retina model. Additionally, we have characterized a single pixel fabricated using the same 0.18 μm process. This pixel demonstrates an 87.7-% ratio of variance with the temporal software model and operates with a power consumption of 369 nW.

A fractional-order hyperchaotic system that is period in integer-order case and its application in a novel high-quality color image encryption algorithm

A new fractional-order 5D hyperchaotic system based on memristor is constructed in this paper, with the speciality that the system exists chaotic and hyperchaotic states in the fractional-order case, while in periodic state in the integer-order. In addition, it has a variety of special phenomena at fractional-order such as infinite initial value range, parameter-dependent offset-boosting and amplitude control, attractor coexistence, and fractional order complexity greater than integer order. The correctness and feasibility of the system is verified by analog circuit simulation and hardware circuit implementation. Combining this system with image encryption algorithms, two new scrambling algorithms and a diffusion algorithm are proposed. And a high-quality encryption scheme that can be applied to a wide range of color images is proposed. The scheme is found to have excellent security after verification by various security analyses and comparison with other literatures. This paper provides a basis for the superiority of fractional-order chaotic systems and provides new methods in the field of image encryption.

The design of a linear voltage divider based on metal oxide arresters.

In recent years, linearization technology for nonlinear devices has become a hot topic in many fields. In this study, a linear voltage divider based on metal oxide arresters was designed by combining linearization technology and electrical measurement technology to solve the objective problems of online voltage monitoring. These problems include high difficulty in equipment installation, low measurement accuracy, and poor economic benefits. Based on a summary of linearization theory, the sufficient and necessary conditions for the linearization of the voltage divider were deduced in detail. The relevant circuit simulations were conducted, along with voltage divider experiments under power frequency AC voltage, operating overvoltage, and lightning overvoltage. The results revealed that the voltage divider was able to realize linearized measurements and meet the relevant standards of online voltage monitoring. The measurement errors were concentrated in the transition region between the pre-breakdown region (small current region) and the breakdown region (nonlinear region) in the volt-ampere characteristic curve. The main influencing factor of errors was the consistency of the nonlinear characteristics of the high- and low-voltage arms of the voltage divider. The voltage divider designed in this study can be applied in many scenarios, such as power plants, substations, high-voltage electrical equipment manufacturing plants, and high-voltage laboratories.

From Finite Element Simulations to Equivalent Circuit Models of Extracellular Neuronal Recording Systems Based on Planar and Mushroom Electrodes.

define a new methodology to build multi-compartment lumped-elements equivalent circuit models for neuron/electrode systems. the equivalent circuit topology is derived by careful scrutiny of accurate and validated multiphysics finite-elements method (FEM) simulations that couple ion transport in the intra- and extracellular fluids, activation of the neuron membrane ion channels, and signal acquisition by the electronic readout. robust and accurate circuit models are systematically derived, suited to represent the dynamics of the sensed extracellular signals over a wide range of geometrical/physical parameters (neuron and electrode sizes, electrolytic cleft thicknesses, readout input impedance, non-uniform ion channel distributions). FEM simulations point out phenomena that escape an accurate description by equivalent circuits; notably: steric effects in the thin electrolytic cleft and the impact of extracellular ion transport on the reversal potentials of the Hodgkin-Huxley neuron model. our multi-compartment equivalent circuits match accurately the FEM simulations. They unveil the existence of an optimum number of compartments for accurate circuit simulation. FEM simulations suggest that while steric effects are in most instances negligible, the extracellular ion transport affects the reversal potentials and consequently the recorded signal if the electrolytic cleft becomes thinner than approximately 100 nm. the proposed methodology and circuit models improve upon the existing area and point contact models. The coupling between the extracellular concentrations and reversal potential highlighted by FEM simulations emerges as a challenge for future developments in lumped-element modeling of the neuron/sensor interface.

Logic-in-memory application of ferroelectric-based WS2-channel field-effect transistors for improved area and energy efficiency

In this study, we applied ferroelectrics to the gate stack of Field Effect Transistors (FETs) with a 2D transition-metal dichalcogenide (TMDC) channel, actively researching for sub-2nm technology node implementation. Subsequently, we analyzed the circuit characteristics of Logic-in-Memory (LiM) operation and utilized LiM features after applying ferroelectrics to achieve a single-device configuration. Based on well-calibrated simulations, we performed compact modeling in a circuit simulator to depict the temperature-dependent electrical characteristics of ferroelectric FETs with a double gate structure and 2D channel (DG 2D-FeFET) in sub-2nm dimensions. Through this, we have confirmed that the 2D FeFET-based LiM technology, designed for the 2 nm technology node, exhibits superior characteristics in terms of delay, power/energy consumption, and circuit area under all temperature conditions, compared to the conventional CMOS technology based on 2D FETs. This verification serves as proof of the future technological potential of 2D-FeFET in extremely scaled-down technology nodes.

Coexisting firing patterns and attractor selection in memristive synapse coupled heterogeneous neurons

In this paper, we present a novel heterogeneous neuron network involving the coupling of a two-dimensional (2D) continuous Rulkov model with a 2D Hindmarsh-Rose (HR) neuron via memristive synapse. The present memristive coupled neuron network can produce an infinite number of coexisting hidden attractors with the same shape but located at different positions in the phase space, resulting in the interesting phenomenon of hidden homogeneous extreme multistability. Firstly, we study complex dynamical behaviors in detail through bifurcation diagrams, Lyapunov exponents, time series and phase portraits. Secondly, to select the desired firing pattern, a control method based on the feedback term is applied to the model. It is observed that the addition of this space-dependent feedback term to the dynamic equation of this model effectively eliminates all undesired firing patterns among the coexisting ones, and drives the heterogeneous neuron network to transition from coexisting hidden firing patterns to the expected firing pattern. Finally, Multisim circuit simulation is performed and the results are in line with numerical simulation.

Numerical Extraction of the Equivalent Circuit for a Basic Magnetoelectric Dipole Antenna

Magnetoelectric dipoles have attracted global research attention due to its broadband, unidirectional, and high front-to-back ratio characteristics. This study implemented a co-simulation between a basic magnetoelectric dipole and its front feeding circuit through the step-by-step numerical extraction of its equivalent circuit model equipped with lumped and frequency-independent components. First, the series resonance subcircuit was derived from the series resonance point in the impedance of the magnetoelectric dipole. Second, the parallel resonance sub-circuit was achieved based on the parallel resonance point. By combining the series and parallel sub-circuits according to the sequence of their resonance frequency, the final form of the equivalent circuit for the basic magnetoelectric dipole was realized. Furthermore, to obtain the component values of the proposed circuit, a numerical fitting technique was adopted to accurately match the input impedance of the antenna and its equivalent circuit. A comparison of the circuit and antenna electromagnetic simulations showed that they agreed well with each other. Hence, the correctness and feasibility of the extraction process were verified. The overall results showed that the proposed circuit model can easily substitute for a basic magnetoelectric dipole in the implementation of antenna/circuit cosimulation in circuit simulators.

Biphasic action potentials in an individual cellular neural network cell

Hardware circuit that can effectively simulate biological neurons is an important basis for neuromorphic computation. Cellular neural network (CNN) cell is the basic information processor of a CNN, which acts like a neuron in the brain and has good circuit realizability. An individual memristive CNN cell is constructed by using a memristor instead of a linear resistor for imitating the ion channel time-varying conductance, in which abundant biphasic chaotic and periodic spiking activities are uncovered. This provides a new way to simulate biological neurons at the level of analog circuits. This paper first deduces the mathematical model of the memristive CNN cell, analyzes the equilibrium stability and then explores its dynamical behaviors based on numerical simulation. The results display that the different spiking activities can be effectively regulated by the system parameters and excitation parameters. Furthermore, the analog circuit of the memristive CNN cell is designed and the PSpice-based circuit simulations are performed to verify the correctness of the numerical simulations.

Analysis and Simulation of Current Balancer Circuit for Phase-Gain Correction of Unbalanced Differential Signals

The phase and gain imbalance of a balun output can be adjusted by a differential current balancer (DCB) circuit. The performance of DCB circuit, for correcting the phase (gain) imbalance, is analyzed for a wide range of input signal level, and the accuracy is verified with circuit simulation. To illustrate the phase-error/gain-error (PE/GE) correction, a 30–40[Formula: see text]GHz DCB circuit is designed and simulated in a 180-nm CMOS process. The DCB is examined for input PE, [Formula: see text], of [Formula: see text] and input GE, GA, of [Formula: see text][Formula: see text]dB. Analysis and simulation illustrate an output phase error [Formula: see text] of [Formula: see text] and output gain error [Formula: see text] of [Formula: see text][Formula: see text]dB, over frequency range of 20–50[Formula: see text]GHz. The results of DCB circuit for PE (GE) compensation are compared to that of phase-correction technique (PCT) circuit, illustrating the superior phase (gain) imbalance correction of the DCB circuit with lower NF and DC power consumption.

Effect of microstructure and bending angle in cold bend pipe of SA 106B on flow accelerated corrosion behavior in simulated pressurized water reactor secondary circuit water environment

The flow-accelerated corrosion (FAC) behavior at different bending angles in bend pipe in simulated secondary circuit water environment of pressurized water reactor (PWR) was investigated. The results indicated that the FAC rates at different bending angles within the bend pipe strongly depended on the ferrite nanocrystallization degree and the mass transfer coefficients. Ferrite nanocrystallization played a dominant effect on FAC, and the mass transfer coefficient played a secondary role on FAC, causing the maximum FAC rate in bend pipe was transferred to the 45° position on the intrados.

A DC-DC Converter with Switched-Capacitor Delay Deadtime Controller and Enhanced Unbalanced-Input Pair Zero-Current Detector to Boost Power Efficiency

This proposed work introduces a DC-DC converter with Switched-Capacitor Delay Deadtime Controller (SCD-DTC), Digitally Controlled Start-Up Block (DC-SUB), and Enhanced Unbalanced-Input Pair Zero-Current Detector (EUIP-ZCD) that helps to improve the overall power efficiency. It also introduces the discussion of key signal waveforms and the two major optimization flowcharts. This proposed DC-DC converter can simultaneously achieve optimized deadtime (body diode conduction < 3 ns) and almost fully eliminate the phenomenon of reverse inductor current (RIC). Furthermore, it also shows that it can achieve a well-regulated output voltage of 1.8 V with <0.01% of output ripple riding on it. All the post-layout simulation results are carried out using 0.18 µm 1P6M CMOS process using Cadence Virtuoso Spectre Circuit Simulator. The silicon chip area of our proposed work (including the output pad frame) is 1.44 mm2. The chip fabrication was sent out in January 2024 and the return of the measurement dies is expected in March 2024. The post-layout simulation results will no doubt closely resemble the measurement results since the proposed work is mostly controlled by digital blocks.

Estimation of Electrostatic Interaction Energies on a Trapped-Ion Quantum Computer.

We present the first hardware implementation of electrostatic interaction energies by using a trapped-ion quantum computer. As test system for our computation, we focus on the reduction of NO to N2O catalyzed by a nitric oxide reductase (NOR). The quantum computer is used to generate an approximate ground state within the NOR active space. To efficiently measure the necessary one-particle density matrices, we incorporate fermionic basis rotations into the quantum circuit without extending the circuit length, laying the groundwork for further efficient measurement routines using factorizations. Measurements in the computational basis are then used as inputs for computing the electrostatic interaction energies on a classical computer. Our experimental results strongly agree with classical noise-less simulations of the same circuits, finding electrostatic interaction energies within chemical accuracy despite hardware noise. This work shows that algorithms tailored to specific observables of interest, such as interaction energies, may require significantly fewer quantum resources than individual ground state energies would require in the straightforward supermolecular approach.

A behavioral nonlinear modeling implementation for MEMS capacitive microphones

We are highlighting the behavioral nonlinear system-level modeling approach for MEMS capacitive microphones. The combination of finite element modeling and large signal nonlinear circuit modeling provides a strong capability to predict electroacoustical performance for capacitive transductions. Circuit simulation tools such as Cadence Virtuoso have emerged as powerful aids in designing behavioral models in both linear and nonlinear regimes. Typical small signal lumped element models fail to capture the MEMS behavior which changes over pressure and electrical bias conditions. The models described herein capture diaphragm displacement and capacitance change over large pressure ranges for a simply supported circular plate. This can be coupled with the electrostatic force, due to the applied bias voltage, and converted back to pressure, thereby realizing a feedback loop in the circuit model. The nonlinear model capability is extended to predict capacitance-bias behavior and estimate pull-in of the MEMS device. The microphone sensitivity, signal-to-noise ratio, and harmonic distortions are accurately predicted using the nonlinear large signal model when compared to measured microphone data.

Design of Fractional-order Transitional Filters of the Butterworth-Sync-Tuned, Butterworth-Chebyshev, and Chebyshev-Sync-Tuned Types: Optimization, Simulation, and Experimental Verification

This paper presents the optimal and generalized design of three different fractional-order (FO) transitional filters for the first time in the literature. The transitional filters considered are of the FO Butterworth-sync-tuned, the FO Butterworth-Chebyshev, and the FO Chebyshev-sync-tuned types. A metaheuristic swarm intelligence optimizer, namely the Crow Search Algorithm (CSA), helps to achieve the optimal FO filter model that minimizes the magnitude error with the theoretical function. The accuracy of the proposed approximants is examined for 19 different combinations of orders of the constituent filters for each of the three types of FO transitional filters. Comparisons with the modified stability boundary locus-based second-, third-, and fourth-order filter approximants demonstrate the compactness and superior accuracy of the proposed models. The average performance regarding the approximation accuracy, computational time, and convergence of CSA for solving the proposed filter design problems is investigated. Circuit simulations conducted on the OrCAD PSPICE platform for the proposed filter using the current feedback operational amplifier as an active element highlight good matching between the proposed model and theoretical filter function. Experimental validation is also carried out to justify the practical feasibility of the proposed filter with printed circuit board fabricated FO capacitor emulators.

Memristor-CMOS Hybrid Circuits Implementing Event-Driven Neural Networks for Dynamic Vision Sensor Camera.

For processing streaming events from a Dynamic Vision Sensor camera, two types of neural networks can be considered. One are spiking neural networks, where simple spike-based computation is suitable for low-power consumption, but the discontinuity in spikes can make the training complicated in terms of hardware. The other one are digital Complementary Metal Oxide Semiconductor (CMOS)-based neural networks that can be trained directly using the normal backpropagation algorithm. However, the hardware and energy overhead can be significantly large, because all streaming events must be accumulated and converted into histogram data, which requires a large amount of memory such as SRAM. In this paper, to combine the spike-based operation with the normal backpropagation algorithm, memristor-CMOS hybrid circuits are proposed for implementing event-driven neural networks in hardware. The proposed hybrid circuits are composed of input neurons, synaptic crossbars, hidden/output neurons, and a neural network's controller. Firstly, the input neurons perform preprocessing for the DVS camera's events. The events are converted to histogram data using very simple memristor-based latches in the input neurons. After preprocessing the events, the converted histogram data are delivered to an ANN implemented using synaptic memristor crossbars. The memristor crossbars can perform low-power Multiply-Accumulate (MAC) calculations according to the memristor's current-voltage relationship. The hidden and output neurons can convert the crossbar's column currents to the output voltages according to the Rectified Linear Unit (ReLU) activation function. The neural network's controller adjusts the MAC calculation frequency according to the workload of the event computation. Moreover, the controller can disable the MAC calculation clock automatically to minimize unnecessary power consumption. The proposed hybrid circuits have been verified by circuit simulation for several event-based datasets such as POKER-DVS and MNIST-DVS. The circuit simulation results indicate that the neural network's performance proposed in this paper is degraded by as low as 0.5% while saving as much as 79% in power consumption for POKER-DVS. The recognition rate of the proposed scheme is lower by 0.75% compared to the conventional one, for the MNIST-DVS dataset. In spite of this little loss, the power consumption can be reduced by as much as 75% for the proposed scheme.

Analytical studies on third-order chaotic systems with Sprott type nonlinearities and their microcontroller implementation

The evolution of chaos in a generic third-order autonomous mathematical model with nonlinearities described by simple mathematical functions is reported in this paper. The nonlinearities termed as Sprott type nonlinear functions are used in the design of a class of third-order systems exhibiting chaotic behavior. The evolution and confirmation of chaos in their system dynamics is observed through numerical simulation studies of one-parameter bifurcation diagrams and Lyapunov exponents. Analytical solutions are developed for systems with piecewise-linear nonlinear functions. Finally, the microcontroller implementation of the third-order system equations with different nonlinearities and analog circuit simulation results are presented to confirm the numerical and analytical results. Chaos in generic third-order systems studied through numerical, analytical and microcontroller results has been reported in the literature for the first time.

A simple 4D no-equilibrium chaotic system with only one quadratic term and its application in pseudo-random number generator

Simple-form chaotic systems with complex behaviors have always attracted the attention of researchers. This article introduces a novel 4D chaotic system that has only a quadratic nonlinear term as compared with the existing no-equilibrium continuous chaotic ones with two quadratic or higher nonlinearity. Despite the simplicity of its model, this new system exhibits complicated chaotic behaviors. Many interesting phenomena including the coexistence of different hidden attractors, offset boosting and antimonotonicity have been discovered by various numerical analysis such as bifurcation diagrams, Lyapunov exponent spectra, and phase portraits. The further circuit simulation of this new system verifies its feasibility and practicality. Moreover, the new system is applied to construct Pseudo-Random Number Generators (PRNG), following a thorough assessment of its complexity and randomness by sample entropy. The generated numbers are subsequently assessed using 15 statistical tests. The results confirm that the new system can produce unpredictable numbers with high randomness, making it ideal for information encryption.

Recovery following exercise-induced fatigue: Influence of a single heart rate clamped cycling session under systemic hypoxia

ABSTRACT We investigated whether a single heart rate clamped cycling session under systemic hypoxia affects the recovery of physical and psycho-physiological responses from residual fatigue compared to normoxia. On separate occasions, twelve trained males performed a 3-d acute training camp scenario. On days 1 and 3, participants cycled for 60 min at a constant heart rate (80% of ventilatory threshold). On day 2, fatigue was induced through a simulated team game circuit (STGC), followed by a 60-min intervention of either: (1) heart rate clamped cycling in normoxia; (2) heart rate clamped cycling in hypoxia (simulated altitude ~ 3500 m); or (3) no cycling. Countermovement jump height and leg stiffness were assessed before and after every session. Perceptual fatigue was evaluated daily. Compared to baseline, jump height decreased at all timepoints following the STGC (all p < 0.05). Leg stiffness and cycling power output only decreased immediately following the STGC, with a 48% further decrease in cycling power output in hypoxia compared to normoxia (p < 0.05). Perceived fatigue, decreased sleep quality, and increased muscle soreness responses occurred on day 3 (p < 0.05). A single heart rate-clamped cycling session in hypoxia reduced mechanical output without affecting recovery of physical performance and perceptual measures from residual fatigue induced through team sport activity.

Utilizing signal flow graph on multiple feedback amplifiers of NMC and DACFC with emphasis on design space exploration and conversion

SummaryOver a long time, different methods of frequency compensation of multistage amplifiers have been exploited for improvement in the behavior of stabilizing. In the present paper, the step‐by‐step conversion process of the dual active capacitive feedback compensation (DACFC) three‐stage amplifier into the nested Miller compensation (NMC) three‐stage amplifier is presented by a systematic approach and signal flow graphs (SFGs) based on the graph theory rules in graph domain. Also, according to graph rules, the conversion of the multiple feedback amplifier NMC into the multiple feedback amplifier DACFC is investigated in detail in the graph domain. During the conversion process, the difference in the gain‐bandwidth product (GBW) in the two mentioned case study's amplifiers is examined in terms of the graph at the system level. The elimination of two branches in one step of the conversion process of the SFG of the NMC into the SFG of the DACFC leads to a significant improvement in the behavior of GBW. This paper also conducts verification of the design of conventional NMC and DACFC amplifier circuits in HSPICE using 0.35‐μm CMOS technology and compares the circuit simulation results to SFG simulation results. In order to show the correctness of the idea, they are redesigned in HSPICE using 0.18‐μm CMOS technology, and appropriate results are obtained.