Circuit Simulation Research Articles

Modeling of intermodulation in a loaded-line phase shifter based on a polynomial varactor model

Abstract This paper investigates if there is an optimum design of loaded-line phase shifters with respect to phase shift/loss figure of merit (FOM) and linearity. The investigation was performed by comparing six loaded-line phase shifters that were implemented in printed circuit board (PCB)technology with shunt-loaded hyperabrupt varactor-diodes. It was demonstrated that the hyperabrupt varactor’s C-V characteristics must be modeled with high accuracy to predict the nonlinear behavior. A polynomial varactor model was employed and experimentally validated. To extend the range of investigated parameter values, the extracted model was scaled and evaluated further in a circuit simulator. The investigation reveals that for a given varactor-capacitance, the phase shift/loss FOM is improved if the varactor-capacitance is evenly distributed and the unit cell length is much shorter than a quarter wavelength. The study demonstrates that the phase shift/loss depends mainly on the distribution of varactor-capacitance and Q factor. The intermodulation (IM) distortion is primarily proportional to the total varactor-capacitance per unit cell. The study also revealed that an increase in the varactor’s Q factor results in higher IM. Therefore, it is a trade-off between low loss and low IM.

DC characteristics of a dynamic vision sensor's photoreceptor circuit evaluated for event-based sensing in the mid-wave infrared

Forthcoming infrared event-based sensors will have utility in the space-based surveillance domain where they could potentially perform traditional sensing and tracking functions with significantly enhanced temporal resolution and reduced downstream datalink demands and power consumption. As a first step toward extending event-based sensing technology into the mid-wave infrared, a DC simulation of the conventional event-based sensor unit cell's photoreceptor circuit is performed, and the results are compared with measurements of a printed circuit board implementation of the same circuit to assess what design freedom is available to interface the photoreceptor with a mid-wave infrared photodetector. Detailed analysis of the circuit and measurements provides insight into which fundamental properties of the transistors drive the photoreceptor's dynamic range and demonstrates several characteristics that are relevant to mid-wave infrared sensing. These characteristics include the capability to produce a stable, low voltage bias on the infrared photodetector to maximize sensitivity, and that operating the circuit below room temperature increases the photoreceptor's dynamic range. Measurements show that even the simplest implementation of the photoreceptor circuit exhibits a dynamic range of logarithmic compression of 150 dB at room temperature. However, the dynamic range is ultimately limited by the mid-wave infrared photodetector's dark current activation energy, which is significantly lower than the threshold voltage (energy) of the photoreceptor's feedback transistor and, thus, there is an incentive for the photodetector's dark current to be diffusion-limited.

A Programmable Gate Driver Module-Based Multistage Voltage Regulation SiC MOSFET Switching Strategy

Silicon carbide (SiC) metal-oxide semiconductor field-effect transistors (MOSFETs), as a new material, have the advantages of low drain-source resistance, high thermal conductivity, low leakage current, and high switching frequency compared with silicon (Si)-based MOSFETs. Therefore, in many industrial applications, Si MOSFETs have been replaced by SiC MOSFETs. However, as the switching speed increases exponentially, some problems are amplified, the most serious of which is the overshoot of current and voltage. The increase in voltage and current slope caused by high switching speeds inevitably leads to overshoot, oscillations, and additional losses in the circuit. This paper focusses on the actual performance of the optimised switching strategy (OSS) in circuit testing and combines the existing simulation results to verify the practicability of OSS. In this paper, the optimised switching strategy is introduced first, and then, the LTspice model of SiC MOSFET is established in detail and verifies the feasibility of the OSS through half-bridge circuit simulation. Finally, the test platform is built using a programmable gate drive module (2ASC-12A1HP). Through a 400 V/30 A double-pulse test, the practicality of the OSS is verified. The experiments show that the OSS can greatly improve the switching performance of SiC MOSFETs.

Analytical Analysis of Power-Constrained Repeaters’ Insertion in Large-Scale CMOS Chips

As the die area of CMOS integrated circuits continues to increase, interconnects will become dominant in determining the performance of the circuits from the standpoint of speed and power consumption. Uniform repeater insertion is an effective method used to reduce the propagation delay of a signal in long resistive-capacitive lines. However, non-optimal repeaters’ insertion yields non-optimal circuit performance. In this work, we provide a mathematical treatment for optimal repeater insertion with power consumption constraints. In particular, a closed-form expression for the optimum number and size of repeaters is given for a two-stage buffer used as a repeater. The validation of the analytical solution is assessed by means of circuit simulations, by comparing the theoretical optimal number and size of the repeaters to be placed in the long resistive-capacitive line with the simulated values.

Closing the Gap between Electrical and Physical Design Steps with an Analog IC Placement Optimizer Enhanced with Machine-Learning-Based Post-Layout Performance Regressors

The design of integrated circuits in the analog spectrum is intricate due to the signals’ continuous nature. Additionally, it is strongly affected by the physical implementation of their devices and interconnections on the layout, a design task that has stubbornly defied all automation attempts. In this paper, one limitative factor is identified that must be addressed to finally push automation tools into the analog integrated circuit design flow: accurate assessment of post-layout performance degradation. For this purpose, a performance-driven placement generator highly integrated with off-the-shelf tools already adopted by circuit/layout designers, i.e., circuit simulator, verification tools (layout-versus-schematic) and layout extractor, is proposed. Toward maximum post-layout accuracy, this generator promotes an exhaustive simulation-based synthesis, extracting, simulating and verifying the post-layout functional behavior of every candidate floorplan. Additionally, to bypass the time-consuming extractions/simulations and accelerate synthesis, novel post-layout performance regressors based on different highly accurate machine learning techniques are also being developed. The data used to train them can be directly and conveniently acquired from previous precise post-placement simulations. Experimental results over two analog circuit structures show that a set of performance regressors based on tree-based models, while operating on compressed design spaces, allow for the speeding up of synthesis by more than 20×, which represents a step toward an efficient fully automatic performance-driven analog integrated circuit design flow.

Anti-bump control for switched systems with decentralised adaptive event-triggering

A control system may exist bumps during mode transitions and discontinuous control input would seriously affect performance. In this paper, the anti-bump (or bumpless) switching control for triggered and switched systems under injection attacks is studied. This control method combines decentralised adaptive event-triggering mechanism (DAETM) and anti-bump condition. The main work is as follows: First, a DAETM is considered to allocate network resources properly and resist data injection attacks. Then, a data buffer is adopted to consolidate data from decentralised channels for ensuring timely utilisation. In addition, a controller gain condition is presented to achieve the bumpless switching between subsystems. Moreover, by adopting piecewise Lyapunov function method, sufficient conditions are obtained for triggered switched systems to be exponentially stable and anti-bump under injection attacks. Finally, the design method effectiveness is verified by actual circuit simulation.

Design and synchronization control application of a new five-dimensional memristor CNN conservative hyperchaotic system

Abstract Incorporating memristors into a cellular neural network (CNN) and introducing chaotic characteristics can generate in highly complex and unpredictable dynamic behaviors. To advance this research area, this paper proposes a new five-dimensional memristor CNN conservative hyperchaotic system and systematically analyzes its dynamic properties. The analysis content includes equilibrium point analysis, Poincaré sections, Lyapunov exponent spectra, bifurcation diagrams, two-parameter Lyapunov exponent spectra, complexity assessment, homogeneous and heterogeneous extreme multistability, etc. In addition, the simulation circuit for the new system is designed and constructed. The digital circuit of the new system is implemented using a microcontroller (MCU). After running simulations, the experimental results from the analog circuit, digital circuit, and numerical simulation are consistent with each other, demonstrating the feasibility of the circuit implementation. Finally, two different synchronization control strategies are employed to achieve synchronization control within a finite time.

Timepix3: single-pixel multi-hit energy-measurement behaviour

Abstract The event-driven hybrid-pixel detector readout chip, Timepix3, has the ability to simultaneously measure the time of an event on the nanosecond timescale and the energy deposited in the sensor. However, the behaviour of the system when two events are recorded in quick succession of each other on the same pixel was not studied in detail previously. We present experimental measurements, circuit simulations, and an empirical model for the impact of a preceding event on this energy measurements, which can result in a loss as high as 70%. Accounting for this effect enables more precise compensation, particularly for phenomena like timewalk. This results in significant improvements in time resolution — in the best case, multiple tens of nanoseconds — when two events happen in rapid succession.

NOR Gate Based LED Inverter

In this paper, the design and simulation of the LED inverter circuit using NOR gate in Proteus software is described. The aim of the practical is to show that simple digital inverter can be created with the NOR gate which is the universal gate and the LED will be used to show that the logic circuit is working. Incidentally, to turn the NOR gate into an inverter, it simply involves linking both inputs together and that simplifies all the layout. The simulation of the circuit was done using proteus software and as the input of the NOR gate-based inverter is changed the output LED source is also changed, and the functionality of the circuit is proved. The paper includes information about control Nor Gate in inverter configuration, the significance of digital logic circuit in basic electronics, and the utility of the Proteus software within learning and prototyping settings. The outcome supports that a NOR gate can invert depicted input indication and can power an LED in a straightforward, low-priced circuit, which forms the basis of more complicated digital set of rules circuits

Design and performance investigation of tunnel-FET based energy efficient approximate and accurate adders targeted towards low power IoT nodes

Abstract The proliferation of IoT enabled SoCs in state-of-the-art consumer electronics has necessitated the use of beyond CMOS devices for the energy efficient computations and sensing design space. In the low supply voltage (VDD) regime, Tunnel FETs (TFETs) have shown serious potential at VDD less than 0.5 V. However, the inherent structure, characteristic interband tunneling and enhance Miller capacitance in TFETs do not allow the conventional CMOS logic design styles to be universally used for TFET based logic circuits. In this paper, we propose three energy efficient and novel TFET based accurate adder circuits namely, Static Energy Recovery Full adder (SERF), Complementary and Level Restoring Carry Logic Full adder (CLRCL) and Balanced Restoring Carry Logic full adder (BRCL) based on constituent TFET based functional units which do not use the CMOS design style. Further, novel approximate adders have been developed for energy efficient implementation in IoT nodes. The BRCL adder consumes approximately 60% less area and 85.36% and 89.6% less energy in comparison to SERF and CLRCL respectively. The approximate adders in the best and worst case facilitate approximately 92% and 75% savings in area and consumes 71% less power than the BRCL adder. When compared to the standard UMC 45 nm bulk MOSFET based designs, the TFET based accurate adders operate at 25% less energy while the approximate adders consume 40% less. All the circuit simulations have been performed using Spectre Simulator of Cadence and device characterization using 2D-TCAD tool.

Design of Integrator and Comparator based on Digital Integrated

This article discusses the design method of integrator and comparator based on digital integrated circuits and circuit simulation using multisim is used to prove the functionality and performance of the circuits. By studying the advantages of digital circuits a circuit module has been designed which can realize integrator and comparator. This paper describes in detail the functioning and designing steps of the circuit and shows the results after simulation. The advantages, disadvantages and application cases of the design are analyzed through the simulation results. The simulation results show that it can fulfill the needs of various scenarios well.

Design and Signal-Decoding Test Verification of Dual-Channel Round Inductosyn Decoding Circuit

During the in-orbit operation of spacecraft, permanent magnet synchronous motors are commonly used as power sources in the drive mechanisms of solar panel arrays and the high-precision servo control systems based on satellites. Apart from the performance of the motors themselves and the software control algorithms, the accuracy of the entire control system is also influenced by angle sensors used to detect the rotor position of the motors. As a high-precision angular measuring instrument, the inductosyn possesses excellent environmental adaptability and long service life. Effectively utilizing the inductosyn can greatly enhance the performance of servo control systems. To address the complexity of the decoding process for dual-channel round inductosyn-to-digital converters, this paper proposes a design of the decoding circuit for dual-channel round inductosyn based on the parallel-synchronization decoding method of two AD2S1210 Resolver-to-Digital Converter (RDC) decoding chips. The decoding circuit amplifies the excitation signal outputted by the AD2S1210 for driving the round inductosyn, and processes the sine and cosine induction signals outputted by the round inductosyn through filtering, amplification, and other methods; by using analog circuitry, the output signals of the dual-channel round inductosyn are processed to meet the input requirements of the AD2S1210. Finally, through both the Multisim (circuit simulation software Version 14.1) simulation and physical experiments, it was verified that the decoding circuit designed in this paper could process the input/output signals of the dual-channel round inductosyn and AD2S1210, and successfully decoded the analog induction signal of the round inductosyn. This greatly simplifies the signal decoding process for the dual-channel round inductosyn.

NUMA-aware parallel sparse LU factorization for SPICE-based circuit simulators on ARM multi-core processors

In circuit simulators that resemble the Simulation Program with Integrated Circuit Emphasis (SPICE), one of the most crucial steps is the solution of numerous sparse linear equations generated by frequency domain analysis or time domain analysis. The sparse direct solvers based on lower-upper (LU) factorization are extremely time-consuming, so their performance has become a significant bottleneck. Despite the existence of some parallel sparse direct solvers for circuit simulation problems, they remain challenging to adapt in terms of performance and scalability in the face of rapidly evolving parallel computers with multiple NUMA hardware based on ARM architecture. In this paper, we introduce a parallel sparse direct solver named HLU, which re-examines the performance of the parallel algorithm from the viewpoint of parallelism in pipeline mode and the computing efficiency of each task. To maximize task-level parallelism and further minimize the thread waiting time, HLU devises a fine-grained scheduling method based on an elimination tree in pipeline mode, which employs depth-first search (DFS-like) to iteratively search for parent tasks and then place dependent tasks in the same task queue. HLU also suggests two NUMA node affinity strategies: thread affinity optimization based on NUMA nodes topology to guarantee computational load balancing and data affinity optimization to enable effective memory placement when threads access data. The rationality and effectiveness of the sparse solver HLU are validated by the SuiteSparse Matrix Collection. In comparison with KLU and NICSLU, the experimental results and analysis show that HLU attains a speedup of up to 9.14× and 1.26x (geometric mean) on a Huawei Kunpeng 920 Server, respectively.

The Accuracy of the Titan 1+ 10 Hz Global Positioning System for Measures of Time, Distance, and Top Speed

Introduction: Global Positioning System (GPS) technology provide quantifiable data concerning the number and types of movements athletes complete across training session and match player. The Titan 1+ is a novel GPS device that has not been investigated to establish measures of accuracy or reliability. The purpose of this study was to establish device accuracy for metrics including distance, top speed, and time between the Titan 1+ 10 Hz GPS device and criterion measures. Criterion measures include tape measure, stopwatch, and radar gun for measures of distance, time, and top speed, respectively. Methods and Materials: 16 male NCAA collegiate soccer players completed running protocols of varying distances and speeds, including long and short duration straight-line running (100m Run and SLR), tight and gradual change of direction running (COD T and COD G), and a team-sport simulated circuit. Results: The Titan 1+ was not significantly different from tape measured distance during the SLR protocol for 10m jog and all movements speed across 20m and 40m (p < .05). The Titan 1+ was significantly correlated to radar gun top speed measures for all distances and movement speeds during the SLR (p < .01). The Titan 1+ was significantly different from the stopwatch for measures of time accuracy (p < .0001), however significant correlations were identified for all jogging distances (p < .01), the 20m and 40m strides (p < .01), and the 10m sprint (p < .01). COD G and COD T distances were accurately measured between the Titan 1+ and tape measure (p < .05). The Titan 1+ revealed correlations for time measures during jogging and striding during the COD G (p = .001 and p < .0001) and during the COD T (p < .0001 and p< .0001). Device accuracy was established for measure of time during the TSSC (p < .05), with time measures significantly correlated between the Titan 1+ and stopwatch (p < .01). Top speed for the TSSC was significantly different between the radar gun and Titan 1+ device (p = .001), but both devices were significantly correlated (p < .01). Conclusions: The results of the present study indicate that the Titan 1+ demonstrates accurate measures of time, distance, and top speed when compared to criterion measures.

Stochastic Memristor Modeling Framework Based on Physics-Informed Neural Networks

In this paper, we present a framework of modeling memristor noise for circuit simulators using physics-informed neural networks (PINNs). The variability of the memristor that is directly related to the neuromorphic system can be handled with this approach. The memristor noise model is transformed into a Fokker–Planck equation (FPE) from a probabilistic perspective. The translated equations are physically interpreted through the PINN. The weights and biases extracted from the PINN are implemented in Verilog-A through simple operations. The characteristics of the stochastic system under the noise are obtained by integrating the probability density function. This approach allows for the unification of different memristor models and the analysis of the effects of noise.

Characteristics of oxide films on TA16 alloy after long-term exposure in simulated secondary circuit water environment of small modular reactor

Currently, little is known about the characteristics of oxide films on Ti alloys exposed to the secondary circuit water environment of small modular reactors (SMRs). In this study, multiple microstructural characterization techniques were employed to meticulously characterize the oxide film characteristics of the TA16 alloy after 6000 h and 8000 h of exposure to a simulated SMR secondary circuit water environment. The results indicate that the oxide films on the 6000 h specimen are composed of a microcrystalline anatase TiO2 interior layer and a coarse-grained anatase TiO2 exterior layer, while the oxide film on the 8000 h specimen typically consists of a microcrystalline anatase TiO2 inner layer, an NiFe2O4 middle layer, and a coarse-grained anatase TiO2 outer layer. As the corrosion time is extended to 8000 h, the presence of NiFe2O4 oxide particles can be attributed to oxide deposition by the 316L stainless steel autoclave used in the corrosion experiments, which results in the migration of Ni and Fe ions onto the surface of the Ti alloy.

Observing Quantum Measurement Collapse as a Learnability Phase Transition

During a quantum measurement, superpositions of states with different observable properties probabilistically collapse into one with a sharp value of the measured observable. In macroscopic quantum systems, this collapse arises via a continuous measurement-induced phase transition (MIPT) at a critical value of the strength of interaction with the measurement apparatus. MIPTs lie outside established paradigms for equilibrium or nonequilibrium critical phenomena and delineate distinct, stable dynamical and computational phases of matter. Quantum computers enable programmable simulation of the interaction of a measurement apparatus with a dynamical quantum system, to explore MIPT phenomena over a range of system sizes while retaining quantum coherence. Yet, existing experimental protocols rely on fundamentally nonscalable postselection techniques or direct classical simulation of quantum circuits. Here, we report the scalable observation of finite-size scaling evidence for an observable-sharpening MIPT in monitored quantum circuits in a chain of Yb+171 ions in Quantinuum’s H1-1 trapped-ion quantum processor. By leveraging an equivalent description as a statistical physics problem, we implement scalable classical algorithms to infer the value of the measured observable from a single experimental shot. This technique enables a truly scalable protocol to observe observable-sharpening MIPTs in generic classes of circuits that cannot be directly classically simulated and also provides enhanced means to detect and suppress errors in the quantum simulation. Published by the American Physical Society 2024

Efficient memristor accelerator for transformer self-attention functionality

The adoption of transformer networks has experienced a notable surge in various AI applications. However, the increased computational complexity, stemming primarily from the self-attention mechanism, parallels the manner in which convolution operations constrain the capabilities and speed of convolutional neural networks (CNNs). The self-attention algorithm, specifically the matrix-matrix multiplication (MatMul) operations, demands a substantial amount of memory and computational complexity, thereby restricting the overall performance of the transformer. This paper introduces an efficient hardware accelerator for the transformer network, leveraging memristor-based in-memory computing. The design targets the memory bottleneck associated with MatMul operations in the self-attention process, utilizing approximate analog computation and the highly parallel computations facilitated by the memristor crossbar architecture. Remarkably, this approach resulted in a reduction of approximately 10 times in the number of multiply-accumulate (MAC) operations in transformer networks, while maintaining 95.47% accuracy for the MNIST dataset, as validated by a comprehensive circuit simulator employing NeuroSim 3.0. Simulation outcomes indicate an area utilization of 6895.7 μm2\\documentclass[12pt]{minimal} \\usepackage{amsmath} \\usepackage{wasysym} \\usepackage{amsfonts} \\usepackage{amssymb} \\usepackage{amsbsy} \\usepackage{mathrsfs} \\usepackage{upgreek} \\setlength{\\oddsidemargin}{-69pt} \\begin{document}$$\\mu m^2$$\\end{document}, a latency of 15.52 seconds, an energy consumption of 3 mJ, and a leakage power of 59.55 μW\\documentclass[12pt]{minimal} \\usepackage{amsmath} \\usepackage{wasysym} \\usepackage{amsfonts} \\usepackage{amssymb} \\usepackage{amsbsy} \\usepackage{mathrsfs} \\usepackage{upgreek} \\setlength{\\oddsidemargin}{-69pt} \\begin{document}$$\\mu W$$\\end{document}. The methodology outlined in this paper represents a substantial stride towards a hardware-friendly transformer architecture for edge devices, poised to achieve real-time performance.

Regulation and analysis of multi-scroll attractors in a class of memristive Hopfield neural networks with high Lyapunov exponents

Multi-scroll chaotic systems have gained significant attention in recent years. However, there is little research on the chaotic systems of memristive neural networks with multiple complex structural attractors. A class of multi-scroll chaotic systems are designed in this paper, which are based on Hopfield neural network by using memristors as synapses. Implementing synaptic control with memristors at various coupling positions allows for the creation of multiple chaotic attractors with distinct topological structures. The proposed systems exhibit special and irregular shaped attractors, and can generate a fixed number of scrolls. Through analysis we find that the systems have high Lyapunov exponents, indicating strong sensitivity and randomness. Meanwhile, the systems exhibit extremely rich dynamic behaviors, such as symmetric coexistence phenomena. Especially, we observe signal amplitude control and offset boosting phenomena in the systems. In addition, simulation circuits are designed based on such chaotic systems to verify the physical feasibility of the systems.

ResNet Modeling for 12 nm FinFET Devices to Enhance DTCO Efficiency

In this paper, a deep learning-based device modeling framework for design-technology co-optimization (DTCO) is proposed. A ResNet surrogate model is utilized as an alternative to traditional compact models, demonstrating high accuracy in both single-task (I–V or C–V) and multi-task (I–V and C–V) device modeling. Moreover, transfer learning is applied to the ResNet model, using the BSIM-CMG compact model for a 12 nm FinFET SPICE model as the pre-trained source. Through this approach, superior modeling accuracy and faster training speed are achieved compared to a ResNet surrogate model initialized with random weights, thereby meeting the rapid and efficient demands of the DTCO process. The effectiveness of the ResNet surrogate model in circuit simulation for 12 nm FinFET devices is demonstrated.