Simple Processor Research Articles

AsAP: A Fine-Grained Many-Core Platform for DSP Applications

Many emerging and future applications require significant levels of complex digital signal processing and operate within limited power budgets. Moreover, dramatically rising VLSI fabrication and design costs make programmable and reconfigurable solutions increasingly attractive. the ASAP project addresses these challenges with a chip multiprocessor composed of simple processors with small memories, achieving high energy efficiency and throughput in a small chip area.

SIMDE: An educational simulator of ILP architectures with dynamic and static scheduling

AbstractThis article presents SIMDE, a cycle‐by‐cycle simulator to support teaching of Instruction‐Level Parallelism (ILP) architectures. The simulator covers dynamic and static instruction scheduling by using a shared structure for both approaches. Dynamic scheduling is illustrated by means of a simple superscalar processor based on Tomasulo's algorithm. A basic Very Long Instruction Word (VLIW) processor has been designed for static scheduling. The simulator is intended as an aid‐tool for teaching theoretical contents in Computer Architecture and Organization courses. The students are provided with an easy‐to‐use common environment to perform different simulations and comparisons between superscalar and VLIW processors. Furthermore, the simulator has been tested by students in a Computer Architecture course in order to assess its real usefulness. © 2007 Wiley Periodicals, Inc. Comput Appl Eng Educ 14: 226–239, 2007; Published online in Wiley InterScience (www.interscience.wiley.com); DOI 10.1002/cae.20154

Outlier Resistance Estimator for GPS Positioning – the Neural Network Approach

One of the popular techniques for solving GPS pseudorange nonlinear quadratic equations to obtain the receiver's position and clock bias involves linearizing the equations and solving them by the least-squares (LS) scheme, which is based on the L2 minimization criterion. When outliers are a problem, LS estimation scheme may not be the best approach because the LS estimator minimizes the mean squared error of the observations. This paper discusses the implementation aspects of L1 and L∞ criteria, and their outlier resistance performance for GPS positioning. Three ordinary differential equation formulation schemes and corresponding circuits of neuron-like analogue L1 (least-absolute), L∞ (minimax), and L2 (least-squares) processors will be employed for GPS navigation processing. The circuits of simple neuron-like analogue processors are employed essentially for solving systems of linear equations. Experiments on single epoch and thereafter kinematic positioning will be conducted by computer simulation for investigating the outlier resistance performance for the least-absolute and minimax schemes as compared to the one provided by the least-squares scheme.

Design and performance evaluation of a Programmable Packet Processing Engine (PPE) suitable for high-speed network processors units

In this paper, we present a Programmable Packet Processing Engine suitable for deep header processing in high-speed networking systems. The engine, which has been – fabricated as part of a complete network processor, consists of a typical RISC-CPU, whose register file has been modified in order to support efficient context switching, and two simple special-purpose processing units. The engine can be used in a number of network processing units (NPUs), as an alternative to the typical design practice of employing a large number of simple general purpose processors, or in any other embedded system designed to process mainly network protocols. To assess the performance of the engine, we have profiled typical networking applications and a series of experiments were carried out. Further, we have compared the performance of our processing engine to that of two widely used NPUs and show that our proposed packet-processing engine can run specific applications up to three times faster. Moreover, the engine is simpler to be fabricated, less complex in terms of hardware complexity, while it can still be very easily programmed.

Special-purpose computing for dense stellar systems

AbstractI'll describe the current status of the GRAPE-DR project. The GRAPE-DR is the next-generation hardware for N-body simulation. Unlike the previous GRAPE hardwares, it is programmable SIMD machine with a large number of simple processors integrated into a single chip. The GRAPE-DR chip consists of 512 simple processors and operates at the clock speed of 500 MHz, delivering the theoretical peak speed of 512/226 Gflops (single/double precision). As of August 2006, the first prototype board with the sample chip successfully passed the test we prepared. The full GRAPE-DR system will consist of 4096 chips, reaching the theoretical peak speed of 2 Pflops.

Scalable Architecture for SoC Video Encoders

Evolving video coding standards demand functional flexibility for implementations, not only at design time but also after fabrication. This paper presents a System-on-Chip design approach with a feasible combination of performance, scalability, programmability, area efficiency, and design time effort for a video encoder. The encoder is based on a homogeneous master-slave processor architecture. Each slave encodes a part of the frame in the Single Program Multiple Data (SPMD) data parallel model. Both shared and distributed memory architectures are presented. Design effort is reduced by identical program codes, automated assembly of software and hardware modules independent of the number and type of processors, as well as our flexible on-chip communication network called Heterogeneous IP Block Interconnection (HIBI). A case study implementation with two to ten simple ARM7 processors, 32-bit HIBI bus and non-optimized processor-independent software gives the performance from 6 to 53 fps for QCIF. The whole encoder area ranges from 173 to 770 kgates excluding the memories. The relation scales reasonably well to systems with more powerful processors and optimized code. The optimization of the communication network shows that with more than six slaves even a serial HIBI connection with 100 MHz speed is feasible. HIBI and the parallelization approach allow exploration and optimization of the communication both at the application and architecture layers.

Fast co-verification of HDL models

This paper presents a method for functional verification of HDL models of digital circuits. The method is based on a co-operation between a simulator and an emulator and utilizes the advantages of both simulation-based and emulation-based verification to form a fast co-verification approach. This is done by verifying the intensive time-consuming part of the circuit in the emulator and the non-synthesizable part as well as the part of the circuit that needs intensive redesign process during the early steps of the design phase in the simulator. To demonstrate the co-verification approach, a tool was developed, which supports Verilog, VHDL, and mixed Verilog–VHDL models. Three benchmarks including a simple 32-bit processor (DP32), a 16-bit arithmetic RISC processor, and a 256-point FFT unit were used in the experiments. The experimental results show that the co-verification approach gives up to 15,000 times speedup for gate-level and up to 100 times speedup for RTL abstractions as compared with the simulation-based verification. Finally, an analytical study on the speedups of the co-verification approach is also presented, which supports the experimental speedups results.

An Overview of Power Analysis Attacks Against Field Programmable Gate Arrays

Since their introduction by Kocher in 1998, power analysis attacks have attracted significant attention within the cryptographic community. While early works in the field mainly threatened the security of smart cards and simple processors, several recent publications have shown the vulnerability of hardware implementations as well. In particular, field programmable gate arrays are attractive options for hardware implementation of encryption algorithms,but their security against power analysis is a serious concern, as we discuss in this paper. For this purpose, we present recent results of attacks attempted against standard encryption algorithms, provide a theoretical estimation of these attacks based on simple statistical parameters and evaluate the cost and security of different possible countermeasures.

Moving from Weakly Endochronous Systems to Delay-Insensitive Circuits

We consider the problem of synthesizing the asynchronous wrappers and glue logic needed for the correct GALS implementation of a modular synchronous system. Our approach is based on the weakly endochronous synchronous model, which defines high-level, implementation-independent conditions guaranteeing correct desynchronization at the level of the abstract synchronous model. We can therefore factor the synthesis problem into (1) a high-level, implementation-independent phase insuring the weak endochrony of each synchronous module and (2) the actual wrapper synthesis phase, highly simplified by the high-level assumptions, yet flexible enough to produce various, efficient implementations.We focus here on the synthesis of delay-insensitive asynchronous wrappers from weakly endochronous synchronous modules, and show how this can be done for a simple DLX processor model.

Static strands

Modern embedded processors are designed to maximize execution efficiency--the amount of performance achieved per unit of energy dissipated while meeting minimum performance levels. To increase this efficiency we propose utilizing static strands , dependence chains without fan-out which are exposed by a compiler pass. These dependent instructions are resequenced to be sequential and annotated to communicate their location to the hardware. Importantly, this modified application is binary compatible and functionally identical to the original, allowing transparent execution on a baseline processor. However, these static strands can be easily collapsed and optimized by simple processor modifications, significantly reducing the workload energy. Results show that over 30% of MediaBench and Spec2000int dynamic instructions can be collapsed, reducing issue logic energy by 16 to 24%, bypass energy 17 to 20%, and register file energy 13 to 14%. Additionally, by increasing the effective capactity of pipeline resources by almost a third, average IPC can be improved up to 15%. This performance gain can then be traded in for a lower clock frequency to maintain a basline level of performance, reducing energy further.

Method for improving acoustic noise attenuation in hand-free devices

The present invention relates to a method for improving acoustic noise attenuation, wherein said method uses a combination which comprises an adaptation control for the partial-band echo compensation process as well as a global-band post-filtration for suppressing residual echo in hand-free devices. This method also uses a level balance (22) as well as a controllable frequency-selection echo compensation (28) with partial-band processing. After the frequency-selection echo compensation (28), the outputted signal is submitted to a post-filtration in another frequency-selection filter (30) using an Wiener-equation adjustment algorithm (Wiener filtration). A single control value (increment vector) is used for controlling both the frequency-selection echo compensation and the other filter. This method can thus be implemented with a very reduced amount of calculations so that it can also be used in simple consumer-directed processors.

GPS Navigation Solutions by Analogue Neural Network Least-Squares Processors

The solution for the receiver's position and clock bias using four or more GPS pseudorange measurements involve nonlinear quadratic equations. One of the popular techniques attempts to linearise the equations and solve them by the least-squares (LS) scheme based on an iterative gradient approach. For real-time applications when the solution is to be obtained within a time of the order of a hundred nanoseconds, a digital computer often cannot comply with the desired computation time, or its use is too expensive. In this paper, two ordinary differential equation formulation schemes and corresponding circuits of neuron-like analog processors will be employed for GPS navigation processing. The circuits of simple neuron-like analog processors are employed essentially for solving systems of linear equations based on the criterion of mean square error minimization, which is commonly utilized for determining positioning solutions in the GPS receivers. Experiments on single epoch and thereafter dynamic positioning will be conducted by computer simulation to validate the usefulness of the proposed scheme. The solutions will be assessed and compared to those provided by the conventional method in which pseudo-inverse matrix calculation by digital computer is involved.

Implementation of the XML linking language XLink by functional methods

This paper is devoted to the construction of processors of a language for describing links between resources in XML documents, which is based on the application of functional programming methods and representation of XML data as S-expressions. An implementation in the high-level functional programming language Scheme, the system SXLink compatible with the XLink specification of the W3 consortium, is considered. A survey and comparative analysis of the existing implementations of the XLink language are given. Typical difficulties associated with the implementation and use of the language are identified, and methods to overcome them are discussed. Examples of the application of the SXLink system to solving problems of processing links between resources in XML documents are considered. An SXLink application program interface based on the use of functions of the Scheme language as first-class objects is suggested. The application of this approach to constructing simple and powerful XLink processors is discussed.

Incorporation of neural network-like processors for GPS navigation

The solution for the receiver’s position and clock bias using four or more GPS pseudorange measurements involves nonlinear quadratic equations. One of the popular techniques for linearizing the equations and solving them is the least squares (LS) scheme based on an iterative gradient approach. For real-time applications when the solution is to be obtained within a time of the order of 100 ns, a computer often cannot comply with the desired computation time, or high-end computers are too expensive. In this paper various ordinary differential equation formulation schemes, and corresponding circuits of neuron-like analog processors, will be described and several tested in order to ascertain their suitability for GPS navigation processing purposes. The circuits of simple neuron-like analog processors are employed essentially for on-line inversion of matrices, which is usually required for determining LS solutions, as well as dilution of precision (DOP) calculation in standard GPS receivers. Data from single epoch and kinematic positioning experiments will be simulated to validate the effectiveness of the proposed scheme. The properties and performance of the proposed scheme will be assessed and compared to those of the conventional method of matrix inversion.

The design of dynamically reconfigurable datapath coprocessors

Increasing nonrecurring engineering and mask costs are making it harder to turn to hardwired application specific integrated circuit (ASIC) solutions for high-performance applications. The volume required to amortize these high costs has been increasing, making it increasingly expensive to afford ASIC solutions for medium-volume products. This has led to designers seeking programmable solutions of varying sorts using these so-called programmable platforms. These programmable platforms span a large range from bit-level programmable field programmable gate arrays to word-level programmable application-specific, and in some cases even general-purpose processors. The programmability comes with a power and performance overhead. Attempts to reduce this overhead typically involve making some core hardwired ASIC like logic blocks accessible to the programmable elements. This paper presents one such hybrid solution in this space---a relatively simple processor with a dynamically reconfigurable datapath acting as an accelerating coprocessor. This datapath consists of hardwired function units and reconfigurable interconnect. We present a methodology for the design of these solutions and illustrate it with two complete case studies: an MPEG2 coder, and a GSM coder, to show how significant speedups can be obtained using relatively little hardware. This work is part of the MESCAL project, which is geared towards developing design environments for the development of application-specific platforms.

Separation of signals from near field noise via pressure and velocity field measurements

The separation of acoustic plane wave signals from near field noise sources is addressed using both pressure and velocity measurements at the same location in the fluid. A compact broadband noise source at a known location is first assumed to generate the noise field. Using a time domain approach a simple signal processor is presented to separate the unknown signal from the noise. Effects of sensor and quantization noise are included in the analysis. A frequency domain analysis of the noise separation approach is presented along with numerical results to illustrate the sensitivity of the method to field point location, noise spectrum, and sensor and quantization noise. The separation of plane wave signals from spatially distributed near field noise sources is then addressed. A signal processor using both pressure and velocity measurements at a single point is developed to separate a plane wave signal from a spectrally pure evanescent noise field generated at a planar interface close to the sensors. Numerical results are presented for several examples to illustrate the noise separation process for a wide range of signals. In particular, the case of overlapping signal and noise spectrums is addressed.

Programming the FlexRAM parallel intelligent memory system

In an intelligent memory architecture, the main memory of a computer is enhanced with many simple processors. The result is a highly-parallel, heterogeneous machine that is able to exploit computation in the main memory. While several instantiations of this architecture have been proposed, the question of how to effectively program them with little effort has remained a major challenge.In this paper, we show how to effectively hand-program an intelligent memory architecture at a high level and with very modest effort. We use FlexRAM as a prototype architecture. To program it, we propose a family of high-level compiler directives inspired by OpenMP called CFlex . Such directives enable the processors in memory to execute the program in cooperation with the main processor. In addition, we propose libraries of highly-optimized functions called Intelligent Memory Operations (IMOs) . These functions program the processors in memory through CFlex, but make them completely transparent to the programmer. Simulation results show that, with CFlex and IMOs, a server with 64 simple processors in memory runs on average 10 times faster than a conventional server. Moreover, a set of conventional programs with 240 lines on average are transformed into CFlex parallel form with only 7 CFlex directives and 2 additional statements on average.

Successive bit‐vector search algorithm for celp vocoders

In this paper, we propose a successive bit‐vector search approach to reduce the computational complexity of coded excited linear predictive coding (CELP) speech coders. By decomposing each codevector into several bit‐vectors, the convolution process of the linear predictive coding model can be simplified. With a suggested matching criterion, the proposed method removes a portion of unlikely codevectors in a bit‐vector by bit‐vector fashion. Theoretical analyses and simulation results show that the proposed search method reduces a lot of the computational load for general codebook searches and maintains nearly the same speech quality as the traditional search approach. The proposed method, which reduces the complexity of the CELP speech coders in VLSI realization, can be flexibly embedded with a simple RISC processor to achieve a low‐cost speech coder.

DOP – A Simple Processor Core for Educational Purposes

A simple 16-bit processor core called DOP suitable for embedded systems is presented. The core was implemented in the Xilinx FPGA devices. The DOP processor illustrates the fundamental principles of computer organization and is therefore used in the introductory hardware course. This paper presents the description of the core, its implementation as well as the description of tools and teaching methodology.

MiniMIPS

We developed the project presented in this paper for an undergraduate computer architecture course specifically aimed at non-engineering students. The project is designed to develop understanding of processor organisation at the functional unit level by building a series software execution driven simulators, from a single cycle sequential processor to a simple pipelined processor. The students are lead through the functional design process step by step, in a succession of carefully structured tasks. The project starts by building functional units of a processor. These units are then used to construct a single cycle processor, a multi cycle processor, and finally a pipelined processor with data hazard detection and forwarding. The main goal of the project is to give students a true insight into the fundamental ideas, which are the basis of the development of the modern microprocessor.