Abstract
AbstractThis article presents SIMDE, a cycle‐by‐cycle simulator to support teaching of Instruction‐Level Parallelism (ILP) architectures. The simulator covers dynamic and static instruction scheduling by using a shared structure for both approaches. Dynamic scheduling is illustrated by means of a simple superscalar processor based on Tomasulo's algorithm. A basic Very Long Instruction Word (VLIW) processor has been designed for static scheduling. The simulator is intended as an aid‐tool for teaching theoretical contents in Computer Architecture and Organization courses. The students are provided with an easy‐to‐use common environment to perform different simulations and comparisons between superscalar and VLIW processors. Furthermore, the simulator has been tested by students in a Computer Architecture course in order to assess its real usefulness. © 2007 Wiley Periodicals, Inc. Comput Appl Eng Educ 14: 226–239, 2007; Published online in Wiley InterScience (www.interscience.wiley.com); DOI 10.1002/cae.20154
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