Simple Inverter Research Articles

A CMOS integrated pulse mode alpha-particle counter for application in radon monitoring

A custom integrated circuit for detecting alpha particles for application in the monitoring of radon has been designed and tested. The design uses the reverse-biased well to substrate capacitance of a p-n junction in a conventional CMOS process as a sense capacitor for incident alpha particles, A simple CMOS inverter is used as an analog amplifier to detect the small potential change induced by an alpha-particle strike on the sense capacitor. The design was implemented in a 1.2-/spl mu/m conventional CMOS process with a sense capacitor area of 110 /spl mu/m/sup 2/. Tests carried out under vacuum conditions using a calibrated /sup 241/Am alpha-particle source showed an output voltage swing of /spl ges/2.0 V for an alpha event. The detector is also shown to have good immunity to noise and high-quantum efficiency for alpha particles.

Complementary Josephson Junction circuits

We present simple Complementary Josephson Junction circuits using 1 kA/cm/sup 2/ Nb junctions. We use long, sine-shaped junctions in order to achieve gain and suppressed side lobes. We have simulated layout-extracted simple inverter and ring oscillator circuits to evaluate the performance of these circuits in 1 kA/cm/sup 2/ technology. Projected gate delays with possible higher critical current density technologies are also simulated. We have experimentally tested the operation of inverter circuits.

PV water pumping with a peak-power tracker using a simple six-step square-wave inverter

The application of photovoltaics (PV) has been increasingly popular, especially in remote areas where power from a utility is not available or is too costly to install. PV powered water pumping is frequently used for agriculture and in households. Among many available schemes, the system under study consists of a PV array, a variable-frequency inverter, an induction motor, and a water pump. The inverter feeds the induction motor, which drives the water pump. To seek the optimum power output of the PV array, the inverter is operated at variable frequency to vary the output of the water pump. The inverter is operated to generate a six-step quasi-square wave instead of a pulse width modulated (PWM) voltage output to reduce the switching losses. The inverter acts as both a variable-frequency source and a peak-power tracker of the system, thus having the number of switches minimized. The system is a low-cost design with a simple control strategy. The direct current (DC) bus is supported by a DC capacitor; thus, a balance-of-power flow must be maintained to avoid the collapse of the DC bus voltage. Another advantage of the system is that the current is limited to an upper limit of the PV array current. Thus, in case a short circuit is developed, the motor winding and the power semiconductor switches can be protected against excessive current flow.

On the lower bounds of CMOS supply voltage

The lower bounds of the supply voltage V DD of ultra-low-power CMOS technologies are investigated under the constraints of standard digital circuit design. After discussing the peculiarities of ultra-low-power CMOS processes, low-voltage device operation, and scaling benefits, the lower limits for V DD are narrowed down from two sides. First, a simple inverter based on idealised transistors is investigated analytically to determine a set of absolute lower bounds of V DD for a set of given design constraints, i.e. minimum gain and noise margins. Next, the feasibility and performance of ultra-low-power CMOS technologies are investigated using process and device simulation, followed by post-processing of the simulated I- V and capacitance data, to determine a set of achievable lower bounds of V DD. On the basis of state-of-the-art processes and special scaling, a set of possible ultra-low-power CMOS processes was developed and numerically analysed on the gate level. These numerical data are then related to the analytical results.

New inverter-driven design and control method for two-phase induction motor drives

A simple inverter circuit is proposed for driving symmetrical and unsymmetrical two-phase induction motors. The inverter provides two-phase independently controlled variable-frequency variable voltages to the primary and auxiliary windings of an induction motor. The dynamic model of the two-phase induction motor driven by the inverter is established. An experimental prototype, which consists of a single-chip microprocessor-based controller, the inverter, and the motor and load, is constructed. Both computer simulation and experimental results show the effectiveness of the proposed inverter-driven motor in achieving higher performance, such as less torque and speed pulsation and reduced vibration and noise, than the conventional motors.

Performance of CMOS ternary full adder at liquid nitrogen temperature

We have designed, implemented and studied the performance at liquid nitrogen temperature (77 K) of a CMOS ternary full adder and its building blocks, the simple ternary inverter (STI), positive ternary inverter (PTI) and negative ternary inverter (NTI), and compared the corresponding performance at room temperature (300 K). The ternary full adder has been fabricated in 2 μm, n-well CMOS through MOSIS. In a ternary full adder, the basic building blocks, the PTI and NTI, have been developed using combinations of a CMOS inverter and transmission gate(s). There is close agreement between the simulated and measured voltage transfer characteristics and noise margins of ternary-valued devices. The measured transient times for the NTI, PTI and ternary full adder at 77 K show an improvement by a factor of ≈1.5–2.5 over the corresponding values at 300 K. The present design does not use linear resistors and depletion-mode MOSFETs to implement the ternary full adder and its building blocks, and is fully compatible with current CMOS technology.

Electronic Characteristics Changes of Semiconductor Devices Caused by Packaging Stress.

The effect of packaging stress on device characteristics was determined experimentally. The sensitivity to stress of the electronic characteristics of MOSFETs was measured by applying uni axial stress to the transistor. The sensitivity to stress was shown to depend on the transistor conduction type and the current flow direction. The packaging stress effect on a simple inverter amplifier using MOSFETs was measured by changing the packaging materials. The residual stress distribution was also measured using stress sensing gauges embedded in LSI chips. The distribution of the amplifier gain change rate agreed well with the residual stress distribution in the LSI chip. The amplifier gain change rate was calculated based on the experimental results of the sensitivity to stress of the electronic characteristics of MOSFETs and the residual stress distribution. This predicted amplifier gain change rate agreed well with the measured data.

Digital characteristics of a CMOS ternary inverter at the liquid nitrogen temperature

Static and dynamic performance of a CMOS ternary inverter has been studied in the MOSFET's threshold voltage region at the liquid nitrogen temperature (77K), and compared with the corresponding room temperature (296K) operation. It is observed that the positive ternary inverter (PTI), simple ternary inverter (STI) and negative ternary inverter (NTI) exhibit sharper voltage transfer characteristics and improved transient response at the liquid nitrogen temperature.

A hybrid static/rotary UPS system

An uninterruptible power supply (UPS) system that employs a rotary converter (motor-generator, or MG, set) as a post conditioner for a simple rugged inverter that can operate either from rectified utility power or batteries to provide regulated sinusoidal power with good transient capacity, low distortion, and complete isolation of the load from the utility is described. A system with total load capacity of 200 kW was constructed using a single inverter to power two induction MG sets: a 125 kVA 60 Hz unit (1800 r/min with flywheel) and a 75 kVA 3600 r/min MG with 400 Hz output. After factory testing, the system was installed at a large computer facility in a location where severe power supply quality problems existed. No instability or other difficulty with multiple MG operation occurred in spite of the size and construction differences between the MG sets.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

簡易高調波低減回路の一方法

簡易高調波低減回路の一方法

Monolithically integrated four-channel receiver array using diffused InGaAs JFET technology

Four-channel receiver arrays have been fabricated by monolithically integrating diffused InGaAs JFET-based electronics with InGaAs pin photodiodes. Cascode and simple inverter transimpedance amplifier circuits have been produced, both of which use a micro-FET as a tunable feedback element to vary bandwidth between 20 and 800 MHz. A sensitivity of –28.2dBm was achieved at 1.25Gbit/s with crosstalk between adjacent channels of –50dB (electrical).

Circuit performance of CMOS technologies with silicon dioxide and reoxidized nitrided oxide gate dielectrics

The circuit performance of CMOS technologies with silicon dioxide (SiO/sub 2/) and reoxidized nitrided oxide (RONO) gate dielectrics over the normal regime of digital circuit operation, i.e. V/sub GS/<or=5 V and B/sub DS/<or=5 V, is discussed. The simulation of a simple CMOS inverter has shown that the SiO/sub 2/ inverter consistently outperforms the RONO inverter over temperatures ranging from 300 to 100 K. This can be attributed mainly to the significantly lower mu /sub p/ (hole mobility) of RONO p-channel devices. At 300 K, mu /sub p/(RONO) is 14-8% smaller than mu /sub p/(SiO/sub 2/) over the entire range of gate biases, while mu /sub n/(RONO) (electron mobility of n-channel RONO devices) is also smaller than mu /sub n/(SiO/sub 2/) and reaches only 96% of mu /sub n/(SiO/sub 2/) at V/sub GS/=5 V. At 100 K, mu /sub n/(RONO)/ mu /sub n/(SiO/sub 2/) at V/sub GS/=5 V is increased to 1.10, however, mu /sub p/(RONO)/ mu /sub p/(SiO/sub 2/) at V/sub GS/=5 V is degraded to 0.59. The dependence of circuit performance on the supply voltage has also been evaluated for the RONO and SiO/sub 2/ inverters.<<ETX>>

An accurate and efficient delay time modeling for MOS logic circuits using polynomial approximation

A delay model for multiple delay simulation for NMOS and CMOS logic circuits is proposed. For the simple inverter the rise or fall delay time is approximated by a product of polynomials of the input waveform slope, the output loading capacitance, and the device configuration ratio, with the polynomial coefficients determined so as to best fit the SPICE simulation results for a given fabrication process. This approach can easily be extended to the case of multiple-input transitions. The simulation results show that the proposed modes can predict the delay times within 5% error and with a speedup of three orders of magnitude for several circuits tested as compared with the SPICE simulation.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Low power dynamic ternary logic

A new dynamic ternary logic and its circuit structures have been developed to achieve the goal of low power dissipation and high operation speed. Based on the selected ternary algebra, a dynamic ternary logic system can be implemented by simple ternary gates (STGs), with positive or negative ternary inverters connected to all the input terminals. An overlapped four-phase clocking scheme is needed, and the connection of different circuit blocks has to follow the permitted fan-out diagrams. As compared to the static ternary logic, the dynamic ternary logic has a lower DC power dissipation and an operation speed approximately twice as fast. Typical powerdelay product of a simple ternary inverter in 2 µm CMOS is 3 fJ. Moreover, as compared with binary circuits, the ternary circuit has better performances of the power-delay product and less terminal leads per functional circuit. These features make the dynamic logic circuits quite attractive in VLSI/ULSI applications.

Improved negative feedback technique to reduce drain conductance of GaAs MESFETs for precision analogue ICs

An improved negative feedback technique to reduce the absolute magnitude of the frequency-dependent drain conductance inherent in GaAs MESFETs has been demonstrated for low-threshold (less than ?1 V) devices. The new dual-threshold arrangement guarantees that the primary device of the self-bootstrapping pair operates at the current saturation region without relying on the existence of early saturation. A factor of 11 reduction in the drain conductance was realised. A simple inverter amplifier of identical composite driver and load has demonstrated 21 dB improvement in voltage gain over that using single FETs.

An RC filter for automatic differential potentiometry

A new differential potentiometric technique based on a simple RC phase inverter circuit that can be used in a variety of automated applications for specific experimental requirements in an analytical laboratory.

Electrical Characteristics of Large-Scale Integration Silicon MOSFET's at Very High Temperatures,Part III: Modeling and Circuit Behavior

The effects of high temperature (27°C to 300°C) on electrical characteristics of long n and p channel metal-oxide semiconductor fieldeffect transistors (MOSFET's) are used to extend the validity of the conventional (room temperature) large and small signal models of these devices. A complementary metal-oxide semiconductor (CMOS) inverter's transfer characteristics and switching speed performance, and the frequency response of a simple resistive load inverter are presented, with temperature as a parameter. Some implications of the models developed, on analog MOS circuit design (for high-temperature, operation), are discussed.

A Simple Multi-Motor Drive with Converter-Fed Synchronous Machines with AC-Excitation

Based on the principles of the well-known converter-fed synchronous machine with DC-excitation, the converter-fed synchronous machine with AC-excitation was developped. This machine is fed by a simple current-fed thyristor inverter without any forced commutation circuits. Due to the AC-excitation there are no commutation problems within the entire speed range down to standstill. Control of the converter and measurement of speed and torque can be accomplished by electronic circuits without mechanical sensor. In this paper a very simple multi-motor drive with these machines for use in cranes, in paper-making or sheet-metal industries is presented. The machines are excited by mains and their stators are connected in parallel and fed by one common thyristor converter without forced commutation circuits. Due to the parallel connection all machines do have the same speed. However, this connection may cause stability problems for the machines. This paper shows, how these problems can be avoided by simple means and a prototype drive with three motors of 25kW each is presented.

A charge-pumping-loop concept for static MOS/RAM cells

A novel bistability concept based on a charge-pumping loop is presented. The loop consists of a charge pump and a simple two-device inverter. With an additional select transistor, the loop can be used as a static MOS/RAM cell. The proposed cell configurations are realized with only four devices, one or two shared supply lines, and an address-bit line pair. Feedback is accomplished with a single non-cross-coupled path. These cells can be manufactured with any industry-standard technology in a considerably smaller silicon area in comparison with the conventional flip-flop configuration. The standby power-dissipation level of the cells is also sufficiently low to meet the objectives of the high-density RAM design.

Radiation-Hardened Silicon-Gate CMOS/SOS

High performance, radiation hardened silicon gate CMOS/SOS circuits have been fabricated. Radiation hardness was achieved by using a low temperature (875°C), wetprocess gate oxide, and by minimizing the temperature of subsequent process steps. The need for additional temperature steps was eliminated by in-situ doping of the polysilicon gate material with boron and by using ion-implantation instead of diffusions to form source and drain regions. Radiation effects in simple inverter circuits have been measured. Threshold shifts after 106 rads (Si) of ionizing radiation are #x02264;0.5 V for n-channel transistors and #x02264;1. 6 V for p-channel transistors. Irradiation of p-channel transistors in circuit configurations where effective positive gate voltages occur, results in a 4 V shift at 106 rads (Si). Ring oscillator circuits have been fabricated to measure intrinsic circuit performance. With a 15 V power supply, stage delays of 0.5 ns are achieved. These short stage delays verify the suitability of the fabrication process for high speed circuit applications.