Simple Clock Research Articles

The role of technology in modern industrial processes: a comparative analysis of automated, automatic and mechanical systems

In the modern technological sphere, systems are categorized into various types based on their level of complexity and functional capabilities. The primary types are mechanical, automatic, and automated systems. Each of these types has its unique characteristics and areas of application. Mechanical systems are the simplest of all. They consist primarily of physical components such as gears, levers, and springs, which interact to perform specific tasks. These systems typically lack built-in control or regulation mechanisms, and their operation is based on basic mechanical principles. Examples of mechanical systems include simple clock mechanisms or traditional measuring devices. Automatic systems represent an evolutionary step beyond mechanical systems, as they include elements for automatic control. These may be electrical or electronic components that enable the system to perform certain operations without direct human intervention. For example, automatic doors or thermostats that regulate room temperature are examples of such systems. They can respond to changing conditions and perform tasks based on predefined parameters. Automated systems, in turn, are the most complex and integrated. They combine automatic control with software and advanced management systems, allowing them to adapt to changing environmental conditions and make decisions independently. Automated systems may include elements of artificial intelligence and machine learning, enabling them to perform complex tasks such as data processing or optimizing production processes. Examples include industrial robotic lines or management systems in distribution networks. Thus, the main differences between these systems lie in their level of complexity and functional capabilities: mechanical systems are based on simple physical principles, automatic systems contain elements of automatic control, and automated systems provide a high level of integration and autonomy.

Quantum time dilation in a gravitational field

According to relativity, the reading of an ideal clock is interpreted as the elapsed proper time along its classical trajectory through spacetime. In contrast, quantum theory allows the association of many simultaneous trajectories with a single quantum clock, each weighted appropriately. Here, we investigate how the superposition principle affects the gravitational time dilation observed by a simple clock – a decaying two-level atom. Placing such an atom in a superposition of positions enables us to analyze a quantum contribution to a classical time dilation manifest in spontaneous emission. In particular, we show that the emission rate of an atom prepared in a coherent superposition of separated wave packets in a gravitational field is different from the emission rate of an atom in a classical mixture of these packets, which gives rise to a quantum gravitational time dilation effect. We demonstrate that this nonclassical effect also manifests in a fractional frequency shift of the internal energy of the atom that is within the resolution of current atomic clocks. In addition, we show the effect of spatial coherence on the atom's emission spectrum.

Mindful aging: an insightful examination of cognitive impairment in the elderly population of Chengalpattu, Tamil Nadu, using Mini-Cog scale

Background: By 2050, United Nations projects that one in five Indians would be 60 years of age or older. This demographic transition is likely to be accompanied by substantial rise in prevalence of cognitive problems, which will have an impact on quality of life among elderly people. Effective screening at primary level would help in identification of burden of diseases and better planning at secondary and tertiary level. Methods: A community-based cross-sectional study over a period of three months was conducted at Pulipakkam in Chengalpattu district. The estimated sample size was 215, and simple random sampling method was used. Elderly people aged 60 years and above who consented to participate were included in the study. After obtaining informed consent, they were screened using the Mini-Cog tool which combines a short memory test with a simple clock- drawing test followed by a recall component. Results: The 215 participants in total were screened. The mean age of participants was 66.02±3.83 years. The prevalence of cognitive impairment (CI) based on Mini-Cog scale was 44.2%. Females (44.8%) had marginally higher prevalence than males (43.8%). CI was more prevalent among people over 65 years (57.6%). The likelihood of experiencing CI was higher among those who lived without their spouse (59.4%), were unemployed (53.7%), and who were smokers / alcoholics (63.7%). Conclusions: Considering the high burden of CI, there is need for long term prospective research for a comprehensive profile of mental disorders at community level. Early assessment and detection of CI could help in improving quality of life of elderly. Implementing initiatives aimed at increasing awareness, reducing stigma, and conducting widespread screening using reliable tools.

BIST (Built-In Self Test) Memory by Using VERILOG

Built-In Self-Test (BIST) is a technique that allows a set up to check itself for any error on its own. BIST is a screening mechanism that places the testing functions physically with the circuit applications where system reliability is predominant, and “failure is not an option.” The decision to execute a critical mission must be made only if the complete system is running without any error. BIST structures generate pseudo random combinations and output results for an exclusive circuit under test are compared. BIST can be implemented on entire designs, design blocks or structures within design blocks. Memory is a complex architecture (fabrication wise) and used in a large number of applications. BIST is basically used to help in the testing of memory with the help of a few extra pins. In fact, while testing a memory using BIST, applying a simple clock signal along with a few pins helps test the entire memory IC. The proposed BIST enabled RAM is designed using Verilog

A Design of a Dual Delay Line DLL with Wide Input Duty Cycle Range

This article describes a dual-controller dual-delay line delay lock loop (DC-DL DLL). The proposed DLL adopted a dual delay line structure, each delay line was composed of a coarse adjustment and a fine adjustment unit, and the dual delay lines had corresponding control units to reduce the mismatch between the delay lines, and it avoided the complicated design of duty cycle correction (DCC) circuit. A frequency divider was added to divide the input clock to achieve a wider input clock duty cycle adjustment. Additionally, a simple clock synthesis circuit was proposed to synthesize the required clock. The DLL design used the 25 nm process with a voltage of 1.2 V. The simulation results showed that at a working frequency of 1.6 GHz, the peak-to-peak jitter of the DC-DL DLL after locking was approximately 17.61 ps, the maximum output duty cycle error was about 1.3%, and the input duty cycle ranged from 20% to 80%, with a power consumption of 10.06 mW.

Revisiting Fault Adversary Models – Hardware Faults in Theory and Practice

Fault injection attacks are considered as powerful techniques to successfully attack embedded cryptographic implementations since various fault injection mechanisms from simple clock glitches to more advanced techniques like laser fault injection can lead to devastating attacks. Given these critical attack vectors, researchers came up with a long list of dedicated countermeasures to thwart such attacks. However, the security validation of proposed countermeasures is mostly performed on custom adversary models that are often not tightly coupled with the actual physical behavior of available fault injection mechanisms and, hence, fail to model the reality accurately. Furthermore, using custom models complicates comparison between different designs and evaluation results. As a consequence, we aim to close this gap by proposing a simple, generic, and consolidated fault injection adversary model that can be perfectly tailored to existing fault injection mechanisms and their physical behavior in hardware. To demonstrate the advantages, we apply it to a cryptographic primitive and evaluate it based on different attack vectors. We further show that our proposed adversary model can be integrated into the state-of-the-art fault verification tool VerFI. Finally, we provide a discussion on the benefits and differences of our approach compared to already existing evaluation methods.

DAC/ADC-free 4 × 12.9 Gbit/s 65,536-level quantum noise stream cipher secure optical WDM transmission based on delta-sigma modulation.

We propose and experimentally study a novel, to the best of our knowledge, quantum noise stream cipher (QNSC) secure transmission scheme based on the delta-sigma modulation (DSM) technique. The cooperation of the QNSC and DSM mechanisms makes it possible to transmit an ultrahigh-order encrypted signal in the non-return-to-zero (NRZ) on-off keying (OOK) format. The delivery of the NRZ OOK waveform over the fiber link allows us to send and receive signals using digital ports, instead of high-speed and high-resolution digital-to-analog converters (DACs) and analog-to-digital converters (ADCs)in conventional QNSC systems. Meanwhile, clock synchronization can be achieved by using a simple clock data recovery algorithm. The extra clock signal transmission link in conventional QNSC systems is no longer needed. The proposed scheme is also compatible with wavelength division multiplexing (WDM) systems. In this work, 4 × 12.9 Gbit/s plaintext is encrypted to a 65,536-level QNSC signal and then transmitted over a 10-km standard single-mode fiber. The transmitter and receiver are established by commercial 100G QSFP28 optical modules with clock data recovery. This proposed scheme can be easily deployed in commercial systems due to its minimalist implementation architecture and relatively low hardware cost.

Simple Clock Drift Estimation and Compensation for Packet-Level Index Modulation and Its Implementation in LoRaWAN

Low-power wide-area network (LPWAN), which includes the long-range wide-area network (LoRaWAN) protocol, is an enabling technology that satisfy low power consumption and long-range communication. In many applications of LPWAN, an end node (EN) transmits data at regular intervals. Based on this, we had previously proposed the concept of packet-level index modulation (PLIM) to increase the number of information bits transmitted by one data packet. In PLIM, the generation interval between two consecutive packets is split into multiple time slots. Each EN transmits its packet in a specific combination of time slot and frequency channel, which represents the index, to convey additional information bits. To retrieve additional information, the gateway (GW) detects the time slot in which the data packet is being transmitted. Therefore, accurate synchronization between EN and GW is essential. However, clock drift occurs due to the inexpensive real-time clock oscillator on each EN, which results in timing misalignment between each node and the GW. This article proposes a simple clock drift estimation and compensation method for the PLIM. An experimental measurement is performed to model the clock drift. The numerical results obtained using the clock drift model show that it can accurately detect the time slot index under the influence of clock drift. Furthermore, PLIM is implemented on a commercial LoRaWAN node and GW to demonstrate its practicability.

Design Margin Reduction Through Completion Detection in a 28-nm Near-Threshold DSP Processor

This article presents a timing error detection and correction (EDaC) technique optimized for near-/sub-threshold operation to recover energy lost in the conventional signoff margins. The presented EDaC requires no modifications to the processor pipeline and avoids imposing additional hold constraints on monitored paths by instantaneously checking for late activity. Furthermore, two correction methods are discussed: a simple clock gating method and a low cycle overhead clock stretching method. Both provide robust last-minute error prevention. The EDaC is applied in a near-/sub-threshold implementation of the CoolFlux DSP processor and infers only a 2.8% and 2.1% area overhead for the detection and correction, respectively. Silicon measurements validate the EDaC system from 0.25 to 0.7 V (1–200 MHz) and show that it recovers all voltage margins in the near-/sub-threshold region. The design achieves a minimum energy point (MEP) of 8.1 pJ/cycle at 0.34 V and 10 MHz. Here, the EDaC technique reduces the energy consumption by 48%–17.6% with respect to the signoff margins depending on their conservatism, and it enables the processor to operate with only 12% energy overhead compared to its ideal non-margined critical operation point.

Virtual Versus in-Person Frailty Assessments in Older Adults with Hematologic Malignancies

Introduction: Time and resource barriers limit widespread implementation of frailty assessment in oncology practice, and the COVID-19 pandemic has reduced the number of in-person visits. To overcome these barriers, virtual geriatric assessments (GAs) have been developed, but lack important objective performance measures such as gait speed and cognitive tests-measures that are important predictors for poor outcomes in older patients with blood cancers (Liu et al., Blood, 2019; Hshieh et al., JAMA Oncol., 2018). We adapted an in-person frailty assessment to a virtual format that maintained both patient-reported and objective measures.Methods: Our cohort assessed in-person (February 2015 to March 2020; resumed June 2021 to July 2021) included all transplant-ineligible patients aged 75 years and older who presented to DFCI for initial consultation for their hematologic malignancy. On the same day as their initial consult, a research assistant administered to consented patients a screening geriatric assessment that assessed for 42 aging-related health deficits using patient-reported and objective performance measures spanning the domains of function, cognition, comorbidity, and mobility. From this assessment, frailty was measured using both the phenotypic (Fried et al., J Gerontol A Biol Sci Med Sci, 2001) and deficit-accumulation approaches (Rockwood et al., J Gerontol A Biol Sci Med Sci, 2007). The frailty phenotype uses five criteria to define a syndrome (slow gait speed, weakness [grip strength], self-reported exhaustion, low physical activity, and weight loss). The deficit-accumulation method calculates the proportion of deficits present in an individual out of the total number of possible deficits measured.To virtually adapt our assessment (Figure 1), patient-reported items were readily converted to questions administered over video- or teleconference. Of the objective measures, grip strength was replaced with self-reported grip strength. The Clock-in-the-Box test was changed to a simple clock draw that the patient completes and displays to the video camera for scoring. 4-meter gait speed is collected by teaching a caregiver to administer with a stopwatch and a 4-meter strip of ribbon. If video is unavailable, self-reported gait speed is measured instead. We expanded eligibility of virtual assessments to patients aged 70 and older.Geriatricians (C.D., T.H., and J.D.) and oncologists (G.A. and J.D.) reviewed the virtual GA for content validity. We measured the proportion of patients who consented and completed the virtual assessment. We assessed for differences in the distributions of age and frailty between virtual and in-person frailty assessments in patients 75 and older using Fisher exact (age) and Chi-square (frailty) tests.Results: Since starting our virtual frailty assessments in November 2020 through July 2021, 118 patients were enrolled and 89 (75%) completed assessments. Median age was 77.6 years (SD = 4.21), 55 (62%) were male, 38 (43%) had lymphoma, 32 (36%) had leukemia/myelodysplastic syndrome/myeloproliferative disorders, and 19 (21%) had multiple myeloma. Of the 89 who completed virtual assessments, 67 (75%) completed the assessment over video with the remaining 22 (25%) over telephone. For the objective measures, 68 (76%) participants were able to complete the clock draw and 47 (53%) were able to complete the gait speed tests. The distribution of age (p = 0.78) and frailty categories (p = 0.49) in our virtual assessments was similar to that of our in-person assessments (Table 1).Conclusion: We developed and successfully delivered a virtual frailty assessment for older adults with blood cancers and found no evidence that frail patients or patients of the highest age categories were unable to complete them. These data suggest that virtual frailty assessment will allow decentralization of assessments even beyond the pandemic, potentially reaching more older adults with blood cancers. The ability to scale to more patients and measure frailty where it matters most-in their own homes-could help overcome barriers to frailty assessments in busy oncology clinics. Virtual frailty assessments also allow for serial measurement while on treatment to better understand and track the trajectory of frailty in this population. [Display omitted] DisclosuresKim: Alosa Health: Other: Personal Fee; NIH: Other: Grants; Alosa Health: Other: Personal Fee.

Associations between visual hallucinations and impaired visuo-spatial abilities in dementia with Lewy bodies.

Objectives: In dementia with Lewy bodies (DLB) recurrent visual hallucinations (VH) often coexist or occur consecutively to impaired visual perception. Since in-depth neuropsychological testing is time-consuming, and therefore, not routinely performed in clinical settings, we aimed to explore whether standard cognitive screening tests may be helpful to alert a clinician to the presence of VH in DLB by exploring association between visuo-spatial dysfunction and VH. Method: The clock drawing, cube, and pentagons copying items from Montreal Cognitive Assessment and Mini-Mental State Exam and nonmotor Hooper visual organization test (HVOT) have been scored in DLB patients with and without VH using traditional and extended scoring methods. Results: Forty-five of 69 (65%) DLB patients were VH-positive (VH+). VH+ patients performed worse on the clock drawing (8.8/16 vs. 11.9/16, p = .016) with a higher rate of misrepresentation of time (69% vs. 29%, p = .002) and numbers (53% vs. 25%, p = .024). Likewise, VH+ patients performed worse on the HVOT (13.3/30 vs. 15.7/30, p = .009) having more isolated (6.2/30 vs. 4.4/30, p = .012) types of responses compared to VH- patients. Both groups had similar copying ability (p > .05). The VH discriminative accuracy of the clock drawing was comparable to that of the more elaborate test of visual perception, the HVOT. Conclusions: In DLB impaired drawing and visual organization, but not copying ability is associated with the presence of VH. The simple clock drawing test can be helpful to alert a clinician to the possibility of VH in DLB. (PsycInfo Database Record (c) 2021 APA, all rights reserved).

The KK principle and rotational symmetry

The KK principle and rotational symmetry

A 7.8 Gb/s/pin, 1.96 pJ/b Transceiver With Phase-Difference-Modulation Signaling for Highly Reflective Interconnects

This paper presents a phase-difference-modulation transceiver with simple clock recovery for highly-reflective interconnects. By greatly suppressing reflective intersymbol interferences with two new enabling mechanisms, phase–difference modulation enables high-speed data communication through highly-reflective multi-drop channels without utilizing decision feedback equalization. A systematic analytical approach is presented, and provides guidelines on how to determine channel and signaling parameters to exploit the two enabling mechanisms based on a newly derived formula of a single bit response of a channel. In addition, we propose a phase-difference amplifier that relieves the timing constraint of the bit decision at the receiver. By deserializing the received signals using the clock embedded in the received signals, the phase-difference amplifier can greatly reduce the design complexity of the clock recovery circuit. The proposed transceiver was fabricated in 65-nm CMOS technology. In single-ended mode, the transceiver achieved a maximum speed of 7.8 Gb/s/pin at energy cost of only 1.96 pJ/b while overcoming 10 in-band notches without decision feedback equalization. Also, the phase-difference amplifier enables clock recovery at power and area costs of only 0.12 pJ/b and 550 $\mu \text{m}^{2}$ , respectively, in single-ended 6-Gb/s/pin operation.

A novel Schmitt trigger and its application using a single four terminal floating nullor (FTFN)

In this research paper, a simple clock wise and counter clock wise Schmitt trigger employing single four terminal floating nullor (FTFN) with two external resistors is presented. The proposed Schmitt trigger avails CMOS based FTFN and it is extended for the application as a square and triangular wave generator, by adding an external capacitor to it. In addition, the proposed waveform generator provides independent tunability of amplitude of square wave by implementing the passive resistors using MOS transistors which make the circuit to be integrated fully. Finally, the verification of the proposed design is verified using PSPICE to justify the theoretical analysis. Also, post layout simulation and the experimental verification using commercially available current feedback operational amplifier named as ICAD844 based implementation for FTFN are included to confirm the reliability of the circuit.

New Method for Simultaneous Determination of Ascorbic and Acetylsalicylic Acids in Effervescent Tablets

The determination of the real concentration in different pharmaceutical drugs represents a very important goal of the pharmaceutical industry. The main aim of the study was to set up a simple, cheap and rapid method in order to determine both ascorbic and acetylsalicylic acid content of effervescent tablets that could be found on the pharmaceutical market, without preliminary separation or extraction. For this purpose, a very simple and reliable clock method based on two Landolt-type systems of reactions, based on potentiometric techniques, has been developed. The method has been tested on different effervescent tablets which contain ascorbic acid and acetylsalicylic acid in different mixture ratio.

Design of ultra‐low power AES encryption cores with silicon demonstration in SOTB CMOS process

The design of ultra-low power advanced encryption standard (AES) encryption cores for emerging wireless networks and Internet of things systems by combining optimised architectures, a simple clock gating technique and an advanced 65 nm silicon on thin buried oxide (SOTB) CMOS process is presented. The implementation results show that the proposed 2-Sbox AES encryption core requires the smallest number of clock cycles and achieves the lowest power consumption of 0.4 µW/MHz which is 3.3× lower than that of the best previous presented AES encryption core, with a very small area overhead. Moreover, the proposed 1-Sbox AES encryption core consumes very low hardware resources of 2.4 kgates gate equivalent.

Early evolution of the land plant circadian clock.

Summary While angiosperm clocks can be described as an intricate network of interlocked transcriptional feedback loops, clocks of green algae have been modelled as a loop of only two genes. To investigate the transition from a simple clock in algae to a complex one in angiosperms, we performed an inventory of circadian clock genes in bryophytes and charophytes. Additionally, we performed functional characterization of putative core clock genes in the liverwort Marchantia polymorpha and the hornwort Anthoceros agrestis.Phylogenetic construction was combined with studies of spatiotemporal expression patterns and analysis of M. polymorpha clock gene mutants.Homologues to core clock genes identified in Arabidopsis were found not only in bryophytes but also in charophytes, albeit in fewer copies. Circadian rhythms were detected for most identified genes in M. polymorpha and A. agrestis, and mutant analysis supports a role for putative clock genes in M. polymorpha.Our data are in line with a recent hypothesis that adaptation to terrestrial life occurred earlier than previously expected in the evolutionary history of charophyte algae. Both gene duplication and acquisition of new genes was important in the evolution of the plant circadian clock, but gene loss has also contributed to shaping the clock of bryophytes.

The Function-Based Design for Sustainability Method

Over the last two decades, consumers have become increasingly aware and desiring of sustainable products. However, little attention has been paid to developing conceptual design methods that explicitly take into account environmental impact. This paper contributes a method of automated function component generation, and guided down-selection and decision-making based upon environmental impact. The environmental impact of functions has been calculated for 17 of the products found in the Design Repository using ReCiPe scoring in SimaPRO. A hierarchical Bayesian approach is used to estimate the potential environmental impacts of specific functions when realized into components. Previously, product environmental impacts were calculated after a product was developed to the component design stage. The method developed in this paper could be used to provide a criticality ranking based on which functional solutions historically have the greatest risk of causing high environmental impact. The method is demonstrated using a simple clock system as an example. A comparative case study of two phone chargers for use in third-world countries demonstrates the decision-making capabilities of this method, and shows that it is possible to compare the environmental impact of alternative function structures during the conceptual stage of design. With the method presented in this paper, it is now possible to make early functional modeling design decisions specifically taking into account historical environmental impact of functionally similar products.

English

In the domain of High Performance Energy Efficient Computing (HPEEC), the focus of research is shifting toward energy efficient computing or low power VLSI design or green computing. We are applying three different clock gating technique in target design of Gurmukhi Unicode Reader (GUR). These power saving techniques reduce the power dissipation of GUR in significant amount. It has been observed that if we switch to flip flop based clock gating instead of simple clock then we can save 89.6% of clock power and we can save 90.48% of clock power if we switch to latch free clock gating (LFCG) or latch based clock gating (LBCG) in case of all SSTL based logic families. It has been observed that if we switch to flip flop based clock gating instead of simple clock then we can save 23.88% of IO power and we can save 26.59% of IO power if we switch to either LFCG or LBCG in case of SSTL2_II_DCI. It has been observed that if we switch to FFBCG instead of simple clock then we can save 52.38% of total power and we can save 56.67% of total power if we switch to either LFCG or LBCG in case of SSTL2_II_DCI.

Short-distance visible light communication with simple clock data recovery for audio applications

As light emitting diodes (LEDs) of fast response time are wide-spreading in a variety of applications such as displays, lighting, traffic signals, and automobiles, many researches on transferring the data with the visible lights of LEDs have been conducted. This paper describes such a visible light communication system that supports the audio applications at the short distance up to 80 cm and the data bandwidth of 32 kHz. Especially, a simple clock data recovery (CDR) is used to achieve the optimum sampling and compensate for the frequency offset between transmitter and receiver. The proposed CDR obtains three samples per symbol and then adjusts the sampling point properly with the pattern of three samples over the frequency offset range of ±1.5% without changing the operating frequency of a receiver side. In the prototype system, a transmitter is composed of audio encoder, field programmable gate array, LED driver, and LEDs and a receiver consists of photodiode, comparator, field programmable gate array, and audio decoder. At the distance of 50 cm and the data rate of 32 kbps, the measured bit error rates are 0.101 and less than 10−8 without and with CDR, respectively.