Silicon-on-thin-buried-oxide Research Articles

A Sub-μ W Reversed-Body-Bias 8-bit Processor on 65-nm Silicon-on-Thin-Box (SOTB) for IoT Applications

For most Internet-of-Things (IoT) applications, embedded processors typically execute lightweight tasks such as sensing and communication. The typical IoT program senses some information and sends them via a channel, usually a wireless channel with an RF circuit. These IoT nodes often require a system with networking capabilities and a low-power harvester implementation. This brief presents a sub- μW 8-bit processor which is suitable for such IoT applications. The processor implements the Open8 Instruction Set Architecture (ISA) with an 8-bit datapath and 16-bit bus addressing. The chip contains the processor and a 4-KB of Static Random-Access-Memory (SRAM), and is fabricated by the 65-nm Silicon-On-Thin-Box (SOTB) process. The SOTB process is one of the Fully-Depleted Silicon-On-Insulator (FD-SOI) technology. Hence, the ability to control biasing voltages is one of its key advantages to achieve low-power. The experimental results show that the power consumption at the reverse-body bias can reach down to 50-nW with 0.5-V supply voltage and 32-KHz operating clock frequency. The completed microcontroller consists of the Open8 processor, 32-KB of Read-Only-Memory (ROM), 4-KB of SRAM, Serial Peripheral Interface (SPI), SPI programmer, debug module, General-Purpose In-Outs (GPIOs), and UART. The system was tested using an XC7A100T Xilinx Field-Programmable Gate Array (FPGA); it yielded 1.8% of the total FPGA utilization.

Statistical analysis of temperature dependence of worst case static random access memory data retention voltage using extreme value theory

The extreme value theory was adopted to analyze the temperature dependence of the worst case data retention voltage (DRV) in static random access memory (SRAM). It was found that the measured worst case DRV of bulk and fully depleted silicon-on-thin-buried-oxide (SOTB) SRAM follow a Gumbel distribution. By extrapolating the fitted Gumbel distribution, the worst DRV of large capacity SRAM at high temperature was estimated. It was also found that the temperature dependence of the worst case DRV in bulk SRAM diminishes as the capacity increases while that in SOTB SRAM is almost unchanged.

A 2T-MONOS Embedded Flash Macro With 65-nm SOTB Technology Achieving 0.15-pJ/bit Read Energy With 80-MHz Access for IoT Applications

To expand Internet of Things application ranges, ultralow active energy operations are essential in edge devices. Especially, read energy reduction in embedded Flash (eFlash) memory is strongly required to enable real-time sensing with limited energy generated by energy harvesting (EH). In this letter, 1.5-MB and 256-KB 2T-MONOS eFlash macros are developed with 65-nm silicon-on-thin-box (SOTB) technology, adopting low-energy sense amplifier and data transmission circuit techniques which enhance intrinsic advantages of SOTB devices. These macros achieve read energy of 0.15-pJ/bit with 80-MHz random read access capability, which is low enough to utilize EH technologies as energy sources.

A 0.9-V 50-MHz 256-bit 1D-to-2D-based single/multi-match priority encoder with 0.67-nW standby power on 65-nm SOTB CMOS

Although priority encoder (PE) plays a vital role in many applications, they perform poorly with large-sized input data. Our previous work tackles this problem by introducing a so-called one-dimensional-array to two-dimensional-array (1D-to-2D) conversion method, which can effectively handle up to a 4,096-bit PE. Taking advantage of the previous achievement, this paper further explores the benefit of a 1D-to-2D-based multi-match priority encoder (MPE). Specifically, compared with other designs implemented in ASIC and FPGA, the proposed PE and MPE outperformed by 4.4 times and 1.7 times, respectively. A 256-bit MPE chip fabricated in a 65-nm silicon-on-thin-buried-oxide (SOTB) CMOS process was also reported. The measurements showed that at 0.9-V supply voltage, the chip was fully operational at 50 MHz and consumed approximately 140.3 µW. More significantly, by exploiting the clock-gating and reverse back-gate biasing techniques, the standby leakage current at 0.6 V dropped to 1.12 nA, which is equivalent to the 0.67-nW standby leakage power.

Low-Power Floating-Point Adaptive-CORDIC-Based FFT Twiddle Factor on 65-nm Silicon-on-Thin-BOX (SOTB) With Back-Gate Bias

In this brief, a silicon-on-thin-BOX (SOTB) implementation of single-precision floating-point fast-Fourier-transform (FFT) twiddle factor (TF) is presented. The architecture of the proposed TF is developed based on the adaptive method of the coordinate rotation digital computer (CORDIC) algorithm. The 65-nm SOTB technology was chosen because of its ultra-low-power advantage. Furthermore, the back-gate bias technique can be applied on an SOTB chip to adjust the operation for high-performance or low-power requirement. The layout of the SOTB 65-nm TF core is about 22869 gate-count on the die area of 86721 $ \mu \text {m}^{2}$ . The measurement results show that the core reached its highest operating frequency of 55 MHz at the 1.2-V supply voltage (VDD) with the forward back-gate bias (FBB) ≥ 1.5 V. The power and energy consumptions at this point were 1.54 mW and 27.91 pJ/cycle, respectively. The lowest operating VDD was at 0.5 V with the FBB ≥ 0.5 V. In the standby mode, when the clock-gating technique was deployed, the leakage current can be reduced to 0.4 nA at the 0.4 V VDD and −2.5-V reverse back-gate bias (RBB).

A 1.2-V 162.9 pJ/cycle bitmap index creation core with 0.31-pW/bit standby power on 65-nm SOTB

Maximizing the performance during peak workload hours and minimizing the power consumption during off-peak time plays a significant role in the energy-efficient systems. Our previous work has proposed an efficient architecture of a bitmap index creator (BIC) that produced higher indexing throughput than the central processing units and graphics processing units. This paper extends the previous study by focusing on the ASIC implementation of BIC in a 65-nm silicon-on-thin-buried-oxide (SOTB) CMOS process. The fabricated chip could operate at different supply voltages, from 0.4 V to 1.2 V. In the active mode with the supply voltage of 1.2 V, it was fully operational at 41 MHz and consumed 6.68 mW, or 162.9 pJ/cycle. In the standby mode with the supply voltage of 0.4 V and clock gated, the power consumption lowered to 10.6 μW. More significantly, when the reverse back-gate bias voltages are supplied, the standby power deeply reduced to 2.64 nW. This achievement is of considerable importance to the energy-efficient systems.

Reduced variability of drain-induced barrier lowering and subthreshold slope at high temperature in bulk and silicon-on-thin-buried-oxide (SOTB) MOSFETs

The temperature dependence of the variability of drain-induced barrier lowering (DIBL) and subthreshold slope (SS) is experimentally investigated in bulk and fully depleted silicon-on-thin-buried-oxide MOSFETs. Measurement results show that variability of both DIBL and SS is reduced at high temperature. The origins of these new findings are explained and confirmed by device simulations. It is found that reduced variability of DIBL at high temperature originates from randomness along the channel length direction (source–drain asymmetry), while reduced variability of SS at high temperature is mainly influenced by randomness along the channel width direction.

Digitally Assisted On-Chip Body Bias Tuning Scheme for Ultra Low-Power VLSI Systems

Body bias control is one of the most efficient means to reduce leakage power, adjust process variation, and apply performance boost. However, such control incurs a certain power overhead that has to be reduced, especially in ultra low-power systems. In order to exploit the advantages of body bias control while guaranteeing power efficiency, an on-chip control scheme is required. Conventionally, on-chip body bias control relies on the use of digital–analog converters. However, such analog circuits require a high power supply voltage and an additional power source, resulting in a considerable power overhead and an increased system cost. In this paper, an on-chip “Digitally assisted Automatic Body-bias Tuning” (DABT) scheme for ultra low-power systems is proposed and evaluated. The proposed scheme controls the body bias voltage so as to meet the timing constraints of a given target system. Since DABT is based on “Digitally assisted” circuitries, it can decrease the power supply voltage to near-threshold region and, therefore, a significant amount of power overhead can be reduced. The proposed system is fabricated with the 65-nm silicon on thin box (SOTB) process, a fully depleted silicon on insulator technology. We demonstrate that the chip can achieve the expected functionality, even with 0.35 V of power supply voltage, and with only a few micro watts of power overhead. Moreover, the efficiency of the proposed system is evaluated with a MIPS processor, adopted as a case study. According to the obtained evaluation results, the proposed system can enable 80% of leakage reduction while maintaining the frequency required to meet the timing constraints of the adopted target MIPS processor.

Comprehensive analysis of low-frequency noise variability components in bulk and fully depleted silicon-on-insulator metal–oxide–semiconductor field-effect transistor

The low-frequency noise (LFN) variability in bulk and fully depleted silicon-on-insulator (FDSOI) metal–oxide–semiconductor field-effect transistor (MOSFET) with silicon on thin box (SOTB) technology was investigated. LFN typically shows a flicker noise component and a signal Lorentzian component by random telegraph noise (RTN). At a weak inversion state, the random dopant fluctuation (RDF) in a channel is strongly affected to not only RTN variability but also flicker noise variability in the bulk MOSFET compared with SOTB MOSFET because of local carrier number fluctuation in the channel. On the other hand, the typical level of LFN in SOTB MOSFET is slightly larger than that in the bulk MOSFET because of an additional interface on the buried oxide layer. However, considering the tailing characteristics of LFN variability, LFN in SOTB MOSFET can be assumed to be smaller than that in the bulk MOSFET, which enables the low-voltage operation of analog circuits.

Lowering data retention voltage in static random access memory array by post fabrication self-improvement of cell stability by multiple stress application

We propose a new version of the post fabrication static random access memory (SRAM) self-improvement technique, which utilizes multiple stress application. It is demonstrated that, using a device matrix array (DMA) test element group (TEG) with intrinsic channel fully depleted (FD) silicon-on-thin-buried-oxide (SOTB) six-transistor (6T) SRAM cells fabricated by the 65 nm technology, the lowering of data retention voltage (DRV) is more effectively achieved than using the previously proposed single stress technique.

Analysis of Soft Error Rates in 65- and 28-nm FD-SOI Processes Depending on BOX Region Thickness and Body Bias by Monte-Carlo Based Simulations

This paper analyzes how body bias and BOX region thickness affect soft error rates in 65-nm SOTB (Silicon on Thin BOX) and 28-nm UTBB (Ultra Thin Body and BOX) FD-SOI processes. Soft errors are induced by alpha-particle and neutron irradiation and the results are then analyzed by Monte Carlo based simulation using PHITS-TCAD. The alpha-particle-induced single event upset (SEU) cross-section and neutron-induced soft error rate (SER) obtained by simulation are consistent with measurement results. We clarify that SERs decreased in response to an increase in the BOX thickness for SOTB while SERs in UTBB are independent of BOX thickness. We also discover SOTB develops a higher tolerance to soft errors when reverse body bias is applied while UTBB become more susceptible

Transistor-level characterization of static random access memory bit failures induced by random telegraph noise

Bit failure events induced by random telegraph noise (RTN) for silicon-on-thin-buried-oxide (SOTB) static random access memory (SRAM) cells were characterized by directly monitoring the storage node voltage of individual cells, using a device-matrix-array (DMA) test element group (TEG). Correlating the cell-level RTN and failure waveforms with the RTN waveforms of individual transistors that constitute the same cell, RTN of a specific transistor that causes the cell failure was identified.

A 1.36 μW 312–315 MHz synchronized-OOK receiver for wireless sensor networks using 65 nm SOTB CMOS technology

The paper presents a receiver design operating at 312–315MHz frequency band for wireless sensor networks. The proposed architecture uses synchronized on–off-keying (S-OOK) modulation scheme, which includes clock information together with data, providing self-synchronization ability for the receiver without a separate clock and data recovery circuit. In addition, a new technique is also proposed to reduce active time of the RF font-end for better energy efficiency. The receiver architecture is verified by using discrete RF modules and FPGAs, then VLSI design is carried out on 65nm Silicon-On-Thin-Buried-Oxide (SOTB) CMOS technology and simulated using SPICE models to illustrate effectiveness of the proposed architecture. Post-layout simulation shows −58.5dBm sensitivity with 1.36μW and 8.39μW power consumption corresponding to 10kbps and 100kbps data rate, respectively.

A Silicon-on-Thin-Buried-Oxide CMOS Microcontroller with Embedded Atom-Switch ROM

The authors demonstrate an ultra-low-power microcontroller unit (MCU) with an embedded atom-switch ROM, which performs 0.39-V operation voltage and 18.26-pJ/cycle minimum active energy (or 18.26-μW/MHz minimum active power) at 14.3 MHz. The MCU is fabricated using an embedded atom-switch process with a hybrid silicon-on-thin-buried-oxide (SOTB) core and bulk I/O transistors. The atom switch is suitable for an ultra-low-voltage operation because of its high on/off conductance ratio. The SOTB CMOS with a body-bias voltage control realizes a high operation frequency of 40 MHz at 0.54 V and an ultra-low sleep power of 0.628 μW, simultaneously.

(Invited) Ultralow-Voltage Design and Technology of Silicon-on Thin-Buried-Oxide (SOTB) CMOS for High Energy Efficient Electronics in IoT Era

Highly energy efficient CMOS circuits are required in theinternet-of-things (IoT) era since a great number of smallelectronic apparatuses process and communicate data. Ultralow-voltage (ULV) operation of CMOS circuits is effective for significantly reducing the power consumption of the circuits. Although operation at the minimum energy (Emin) point (MEP) is effective, most of the scaled circuits operate with far higher energy than Emin. The silicon-on-thin-buried-oxide (SOTB) CMOS is a strong candidate for ultralow-power (ULP) electronics because of its small variability and back-bias control.[1,2] These advantages of SOTB CMOS enable power and performance optimization with adaptive Vth control at ULV and can achieve ULP operation with acceptably high speed and low leakage. The MEP operation is generally very slow, e.g. less than 1MHz. The variable Vth approach with adaptive back-bias control can mitigate the situation of decreasing energy as low as possible down to MEP while satisfying the required frequency. Another obstacle is the variability of transistors, which degrades operation margin especially at low Vdd. To solve these problems, we are developing silicon on thin buried oxide (SOTB) [3-4]. In this paper, we demonstrate SOTB’s small variability, back-bias control, and ULV circuit operation. SOTB Device Results A cross-section of the SOTB/bulk hybrid CMOS and a TEMphoto are shown in Figs. 1 and 2. The back-bias voltages, Vbn and Vbp, are applied to the well regions below BOX. The local interconnect by the silicide at the well contact region contributes to improving the back-bias voltage stability. Details of the SOTB process and electrical characteristics are described in [3]. Very small Vth and Ion variability was demonstrated [3] for one million transistors The Pelgrom coefficient was ~1.3 mVμm, the smallest level taking the gate-oxidethickness (Tinv = 2.4 nm) into account. With this improvement, we confirmed 6-T SRAM operation (2 Mbit) at less than 0.4 V (Fig.3 (a)) with a 5.5-ps access time and demonstrated that the minimum operating voltage can be controlled at <0.4 V across whole 300mmF wafer (Fig.3 (b)). The back bias control successfully reduced the standby leakage of SRAM to 0.4pA/cell, which meet the requirement of IoT application (Fig.4). Furthermore, we demonstrated the compensation of temperature change or global variability by back bias control [3-4], resulting further improvement of operation margin at low Vdd. SOTB Circuit Design and ULV Operation We developed a standard cell library for the SOTB technology. The SOTB design flow is basically the same as that for the bulk technology. Using our SOTB flow, various logic circuits were designed and ULP operations were confirmed, such as an accelerator [5] and flex-power FPGA with back biasing [6]. We designed a micro-controller chip dedicated to the sensor-node application [7]. This chip operated at Vdd = 0.35 V and consumed only E = 13.4 pJ. The sleep current was only 0.14 μA. We demonstrated sensor-node operation. The CPU was operated with a single PV cell at <0.4 V. Temperature and acceleration were monitored, and only in an emergency (health problems), an alert was sent via Bluetooth low energy (BLE) to a tablet. Acknowledgment This work was performed as “Ultra-Low Voltage Device Project" funded and supported by METI and NEDO.

(Invited) Ultralow-Voltage Design and Technology of Silicon-on Thin-Buried-Oxide (SOTB) CMOS for High Energy Efficient Electronics in IoT Era

We demonstrated ultralow voltage (<0.4V) operation of Silicon-on-Thin-Buried-oxide (SOTB) CMOS. Thanks to the small variability of SOTB Vmin of SRAM was lowered down to <0.4 V. Both fast access time and small standby leakage were achieved by adaptive back biasing (ABB). 32-bit RISC CPU operated at ultralow energy consumption of 13.4 pJ.

Initial and long-term frequency degradation of ring oscillators caused by plasma-induced damage in 65 nm bulk and fully depleted silicon-on-insulator processes

The degradation of reliability caused by plasma-induced damage (PID) has become a significant concern with the miniaturization of device size. In particular, it is difficult to relieve PID in silicon-on-insulator (SOI) because it contains buried oxide (BOX) layers. In this work, we compare PID between a bulk and a silicon on thin BOX (SOTB), which has BOX layers of less than 10 nm. We measure frequencies of ring oscillators with an antenna structure on a single stage. In the bulk, PID is relieved by first connecting an antenna to a drain because electric charge flows to a substrate. The difference in initial frequency is 0.79% between structures, which cause and relieve PID. SOTB also relieves the same amount of PID. Initial frequencies are affected by PID, but there is no effect of PID on the long-term degradation mainly caused by bias temperature instability (BTI).

Detailed analysis of minimum operation voltage of extraordinarily unstable cells in fully depleted silicon-on-buried-oxide six-transistor static random access memory

The minimum operation voltage (Vmin) of very unstable cells in silicon-on-thin-buried-oxide (SOTB) six-transistor (6T) static random access memory (SRAM) is analyzed in detail. It is found that the worst cell in 16k SRAM is very unstable and the stability characteristics of the worst cell correspond to approximately 6σ from those of the median cell. It is also found that extraordinarily unstable cells are much more sensitive to VTH change than median cells and that the static noise margin (SNM) and Vmin well correlate only in extraordinarily unstable cells. A simple VTH model for evaluating Vmin is developed and validated by Vmin measured in extraordinarily unstable cells.

Low-power embedded read-only memory using atom switch and silicon-on-thin-buried-oxide transistor

We developed an atom-switch read-only memory (ROM) fabricated on silicon-on-thin-buried-oxide (SOTB) for use in a low-power microcontroller for the first time. An atom switch with a low programming voltage and large ON/OFF conductance ratio is suitable for low-power nonvolatile memory. The atom-switch ROM using an SOTB transistor uses a 0.34–1.2 V operating voltage and 12 µA/MHz active current (or 4.5 µW/MHz active power). Furthermore, the sleep current is as low as 0.4 µA when a body bias voltage is applied to the SOTB.

Ultralow-Power SOTB CMOS Technology Operating Down to 0.4 V

Ultralow-voltage (ULV) CMOS will be a core building block of highly energy efficient electronics. Although the operation at the minimum energy point (MEP) is effective for ULP CMOS circuits, its slow operation speed often means that it is not used in many applications. The silicon-on-thin-buried-oxide (SOTB) CMOS is a strong candidate for the ultralow-power (ULP) electronics because of its small variability and back-bias control. Proper power and performance optimization with adaptive Vth control taking advantage of SOTB’s features can achieve the ULP operation with acceptably high speed and low leakage. This paper describes our results on the ULV operation of logic circuits (CPU, SRAM, ring oscillator and other logic circuits) and shows that the operation speed is now sufficiently high for many ULP applications. The “Perpetuum-Mobile” micro-controllers operating down to 0.4 V or lower are expected to be implemented in a huge number of electronic devices in the internet-of-things (IoT) era.