Abstract
Ultralow-voltage (ULV) CMOS will be a core building block of highly energy efficient electronics. Although the operation at the minimum energy point (MEP) is effective for ULP CMOS circuits, its slow operation speed often means that it is not used in many applications. The silicon-on-thin-buried-oxide (SOTB) CMOS is a strong candidate for the ultralow-power (ULP) electronics because of its small variability and back-bias control. Proper power and performance optimization with adaptive Vth control taking advantage of SOTB’s features can achieve the ULP operation with acceptably high speed and low leakage. This paper describes our results on the ULV operation of logic circuits (CPU, SRAM, ring oscillator and other logic circuits) and shows that the operation speed is now sufficiently high for many ULP applications. The “Perpetuum-Mobile” micro-controllers operating down to 0.4 V or lower are expected to be implemented in a huge number of electronic devices in the internet-of-things (IoT) era.
Highlights
IntroductionA huge number of small electronic devices composing big data are expected to be used across the globe as the “internet of things” (IoT)
Issues for ULV Operation Possibly Staying on minimum energy point (MEP) PointA huge number of small electronic devices composing big data are expected to be used across the globe as the “internet of things” (IoT)
The energy efficiency of CMOS circuits has been greatly improved by the miniaturization of CMOS transistors
Summary
A huge number of small electronic devices composing big data are expected to be used across the globe as the “internet of things” (IoT). MHz. The variable Vth approach with adaptive back-bias control can mitigate the situation: optimizing frequency and decreasing energy as low as possible down to the MEP value. The variable Vth approach with adaptive back-bias control can mitigate the situation: optimizing frequency and decreasing energy as low as possible down to the MEP value Both Vdd and Vth are controlled to minimize the energy, while satisfying the required workload: required frequency. Another variability tolerant logic design prefers a smaller number of pipeline stages and longer logic depth These design strategies decrease the frequency [10,11] and increase Emin. We hypothesize the main issues for the highly energy efficient CMOS circuits are adaptive Vth control and small variability, as described . We show SOTB’s low voltage capability, including small variability and back-bias control through device and circuit results
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