Silicon-on-insulator Research Articles

Performance Analysis of Gate Engineered High-K Gate Oxide Stack SOI Fin-FET for 5 nm Technology

Abstract: This paper analyses the performance of 5 nm gate length gate engineered oxide stack silicon on insulator (SOI) fin field-effect transistor (OS-Fin-FET) for the first time. The high dielectric (High-K) value of the material-based gate oxide stack structure increases both the analog and the radio frequency (RF) performance of the Fin-FET device when compared to standard single gate oxide material structures. The work function of the engineered gate structure further helps in advancing the performance of the device in terms of on current (Ion), off current (Ioff) and the ratio of Ion/Ioff. The proposed OS-FinFET device improves on current (Ion) of the device by 12% in comparison to the high-K dielectric gate oxidebased FinFET device. Simulation of the device is further extended to study different electrical characteristics of the proposed device under other biasing conditions, to estimate enhanced analog and RF performance where the device is highly suitable for low power and high-speed applications. Overall, the proposed device shows improvement in existing architectures of the devices. Technology computer-aided design (TCAD) tool is used to perform entire simulations of the proposed device with 5 nm gate length. Aim: To enhance analog and RF performance of the Fin-FET device at 5 nm gate length. Background: Design of the sub-10 nm Fin-FET device undergoes charge shearing phenomena because of the minimum distance between source and drain. This problem is addressed by using High-K spacer over substrate but it leads to increase in the channel resistance and adverse short channel effects. A combination of different high-K dielectric materials can eliminate this performance. Hence most of the studies concentrated on spacer region and failed to consider channel region. This study tries to improve analog performance of the device using the approach of gate engineering with gate stack approach. Objective: The main objective of this study is to increase on current (Ion) of the device by implementing gate engineering approach, by choosing dual work function-based gate with oxide stack approach. The High-K dielectric material-based gate oxide reduces leakage current, decreases off current which will increase the ratio of Ion/Ioff. Methods: The dual work function gate material is taken with gate oxide stack approach by considering different High-K dielectric materials like HfO2, TiO2 with thin SiO2 layer as the interactive layer. Simulation of the device is carried out using TCAD Tool and results are compared with existing literature, to validate the results. Results: The proposed architecture of the Fin-FET device delivers excellent results in terms of on current and subthreshold characteristics compared to existing literature. The proposed device gives high on current of 0.027 A and current ratio of 1.08X104. Conclusion: A complete comparative analysis is carried out with existing literature on the proposed device, where the proposed device resulted in high performance. The proposed device improves 12% compared to existing literature, which is highly suitable for low power applications.

16-Channel Wavelength Division Multiplexers Based on Subwavelength Grating

Wavelength Division Multiplexing (WDM) plays an important role in optical interconnection. In this paper, a 16-channel WDM device is designed on a Silicon-On-Insulator (SOI) substrate by using a sub-wavelength grating (SWG) structure, which can cover O-band and C-band at the same time, and the output channel is reversely coupled from the main waveguide to realize wavelength demultiplexing. The simulation results show that the loss of our 16-channel wavelength demultiplexing device is less than 0.5 dB and the crosstalk is less than 17 dB. When WDM is performed in O-band, the transmission loss of the C-band in the bus waveguide is less than 0.05 dB and is insensitive to the grating duty cycle, with good process tolerance. The footprint of the device is 200 μm × 150 μm, and the size of the single-channel filter is 200 μm × 2 μm, which can realize WDM with large bandwidth in a compact structure.

Adjoint optimization of polarization-splitting grating couplers.

We have designed a polarization-splitting grating coupler (PSGC) in silicon-on-insulator (SOI) that has 1.2 dB peak loss in numerical simulations, which is the best simulated performance of PSGCs without a bottom reflector to the best of our knowledge. Adjoint method-based shape optimization enables us to explore complex geometries that are intractable with conventional design approaches. Physics-based process-independent knowledge of PSGCs is extracted from the adjoint optimization and can be transferred to other platforms with a minimum of effort.

High performance nanoscale SOI MOSFET with enhanced gate control

A nanoscale SOI MOSFET structure with enhanced gate control is provided in this article. The gate is positioned in the silicon region's center and surrounded by insulating HfO2 and SiO2. Using this structure, we attempt to enhance the gate control over the channel. Furthermore, the source connection is positioned horizontally within the silicon region to generate an electric field caused by the potential difference between the gate and the source junction in the channel region. In fact, in addition to enhanced control of the gate over the channel, the idea of utilizing gate and source connections within the silicon region has led to the maximum electron temperature shifting from the channel to the drain region. Also, generating an undoped silicon region has been feasible to lower the lattice temperature. In addition, the electrical characteristics of the proposed MOSFET in both DC and AC states will be improved. The electrical features such as effective mobility, hot electron effect, electric field, and self-heating effect have been improved. The proposed structure is designed for RF applications and is studied in the 1 MHz to 500 GHz range. The frequency characteristics of the proposed structure, like the gate-source and gate-drain capacitors, S parameters, maximum unilateral power gain, transducer power gain, minimum noise figure, and noise conductance have also been enhanced.

Electrical performance and noise assessment of vertical ferroelectric tunnel junction based SELBOX TFET

A novel vertical ferroelectric tunnel junction based TFET design with selective buried oxide (SELBOX) is proposed and analytically simulated. The tunneling area is augmented as the tunnel junction remains perpendicular to the channel direction. Moreover, the device drive current boosts up due to the incorporation of ferroelectric material at the tunnel junction along with the n+ pocket. OFF current is restrained at a lower value by releasing the OFF-state charge carriers through the gap in the buried oxide. Through systematic simulation the dimensions of the device architecture are optimized to study its impact on the electrical parameters and to exaggerate the current ratio. An enhanced ION/IOFF current ratio of 4.1 × 1013 with substantially minimum Subthreshold Swing (SS) of 39 mV/decade is achieved. Further, the affectability of different noise components on the device performance has been investigated considering a range of frequency. The proposed TFET design is benchmarked with other existing novel TFETs and is proved to be a better design with improved performance considering ON state current and SS.

Optimization of bulk sensitivity for strip, slot, and subwavelength grating-based waveguides for dual-polarization operation.

We propose a dual-polarization optimization method for the bulk sensitivity of silicon-on-insulator (SOI) waveguides by defining a multi-objective function that accounts for the substrate leakage losses. The proposed optimization method was used to design micro-ring resonator bulk sensors with strip, slot, subwavelength grating, and subwavelength grating slot waveguides. The subwavelength grating slot waveguide has a bulk sensitivity of 520 nm/RIU and 325 nm/RIU for the TE and TM modes, respectively, both of which are higher than the bulk sensitivities of strip, slot, and subwavelength grating waveguides. Moreover, our Monte Carlo analysis shows that the subwavelength grating slot waveguide has the highest immunity to fabrication errors.

Ultra-compact silicon photonics highly dispersive elements for low-latency signal processing.

On-chip optical group-velocity dispersion (GVD) is highly desired for a wide range of signal processing applications, including low-latency and low-power-consumption dispersion compensation of telecommunication data signals. However, present technologies, such as linearly chirped waveguide Bragg gratings (LCWBGs), employ spectral phase accumulation along the frequency spectrum. To achieve the needed specifications in most applications, this strategy requires device lengths that are not compatible with on-chip integration while incurring in relatively long processing latencies. Here, we demonstrate a novel design strategy that utilizes a discretized and bounded spectral phase filtering process to emulate the continuous spectral phase variation of a target GVD line. This leads to a significant reduction of the resulting device length, enabling on-chip integration and ultra-low latencies. In experiments, we show GVD compensation of both NRZ and PAM4 data signals with baud rates up to 24 GBd over a 31.12-km fibre-optic link using a 4.1-mm WBG-based on-chip phase filter in a silicon-on-insulator (SOI) platform, at least 5× shorter compared to an equivalent LCWBG, reducing the processing latency down to ∼ 100 ps. The bandwidth of the mm-long device can be further extended to the THz range by employing a simple and highly efficient phase-only sampling of the grating profile. The proposed solution provides a promising route toward a true on-chip realization of a host of GVD-based all-optical analog signal processing functionalities.

Design and Development of a MOEMS Accelerometer Using SOI Technology.

The micro-electromechanical system (MEMS) sensors are suitable devices for vibrational analysis in complex systems. The Fabry-Pérot interferometer (FPI) is used due to its high sensitivity and immunity to electromagnetic interference (EMI). Here, we present the design, fabrication, and characterization of a silicon-on-insulator (SOI) MEMS device, which is embedded in a metallic package and connected to an optical fiber. This integrated micro-opto-electro-mechanical system (MOEMS) sensor contains a mass structure and handle layers coupled with four designed springs built on the device layer. An optical reading system using an FPI is used for displacement interrogation with a demodulation technique implemented in LabVIEW®. The results indicate that our designed MOEMS sensor exhibits a main resonant frequency of 1274 Hz with damping ratio of 0.0173 under running conditions up to 7 g, in agreement with the analytical model. Our experimental findings show that our designed and fabricated MOEMS sensor has the potential for engineering application to monitor vibrations under high-electromagnetic environmental conditions.

ANN-Assisted High-Resolution and Large Dynamic Range Temperature Sensor Based on Simultaneous Microwave Photonic and Optical Measurements

We proposed and demonstrated a temperature sensor with both high resolution and large dynamic range based on simultaneous microwave photonic and optical measurements. To simultaneously increase the sensitivity and dynamic range of optical measurement, two cascaded ring resonators (CRRs) with different temperature sensitivities and free spectral ranges (FSRs) are designed as the sensing probe and fabricated based on silicon-on-insulator (SOI) wafer. Based on the ultrahigh-Q-factor microring in the CRR, a microwave photonic notch filter (MPNF) is obtained and used to achieve a high temperature resolution. Meanwhile, the optical transmission spectrum of the CRR is used to achieve a large dynamic range. Combining the two measurements, a temperature sensor with both high resolution and large dynamic range is realized. To improve the response speed and robustness of the sensing system, the artificial neural network (ANN) is used to directly extract the temperature from the CRR spectrum, which is particularly helpful at low signal-to-noise ratio (SNR). The sensing resolution and dynamic range achieved by our scheme are <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$7.02 \times 10^{-3}$ </tex-math></inline-formula> °C and 106.94 °C, respectively.

Frequency-selectable microwave generation based on on-chip switchable spectral shaping and wavelength-to-time mapping.

We propose and experimentally demonstrate a scheme for the photonic generation of pulsed microwave signals with selectable frequency based on spectral shaping and wavelength-to-time mapping (WTTM) technique. The frequency selectivity is realized by channel switching on an integrated silicon-on-insulator (SOI) spectral shaping chip. The incident signal is spectrally shaped by the asymmetric Mach-Zehnder interferometer (MZI) in the selected channel, and an optical spectrum with uniform free spectral range (FSR) can be generated in a broad bandwidth up to dozens of nanometers, implying large microwave signal duration after WTTM if a pulse light source with matched bandwidth is available. Microwave pulses of frequency from 3.6 GHz to 28.4 GHz with a fixed interval are experimentally generated respectively. The realization of eight microwave frequencies selectable with only one shared dispersive element (DE) required indicates high expansibility in the frequency cover range of our scheme by tuning the dispersion value in WTTM.

Single-event burnout hardening evaluation with current and electric field redistribution of high voltage LDMOS transistors based on TCAD Simulations

—A single-event burnout (SEB) hardened design based on high voltage lateral double-diffused metal-oxide-silicon (LDMOS) devices with an optimal partial buried oxide (BOX) layer and a N-buffer layer is firstly proposed in this paper. By analyzing the response of surface electric field and transient current, the optimal parameters of hardened layers are selected. Simulation results reveal that an optimal buffer layer can suppress the peak electric field from 4.5 MV/cm to 2 MV/cm, recreate the position of peak electric field and an optimal BOX layer can reconstruct the path of electron and hole currents, reducing the risk of parasitic bipolar-junction-transistor (BJT). By contrast, the SEB triggering voltage can be improved from 197 V to 396 V, with an increase of 100%. And the ratio of safe operating area (SOA) with SEB to breakdown voltage (BV) can be increased from 30% to 69%. In the case of heavy-ions with different energies, the SEB hardened LDMOS also has better performance than the conventional one.

Inverse design of an on-chip optical response predictor enabled by a deep neural network.

We proposed inverse-designed nanophotonic waveguide devices which have the desired optical responses in the wide band of 1450-1650 nm. The proposed devices have an ultra-compact size of just 1.5 µm × 3.0 µm and are designed on a silicon-on-insulator (SOI) waveguide platform. Individual nano-pixels with dimensions of 150 nm × 150 nm were made of either silicon or silicon dioxide, and the materials for the 200 total cells were determined using a trained deep neural network. While training the two networks, the hyperparameter optimization method was applied to make the training process efficient. We then fabricated the proposed devices using a CMOS-compatible fabrication process, and experimentally verified the fabricated device performance.

Comparative of analog performance of transcapacitances in asymmetric self-cascode and graded-channel SOI nMOSFETs

This work presents a comparative study of the transcapacitances of an asymmetric self-cascode (A-SC) and graded-channel (GC) silicon-on-insulator (SOI) nMOSFETs with different gate lengths. This analysis was done by means of two-dimensional numerical simulations. Simulated results show the influence of others transcapacitances on the gate-to-gate capacitance for the ASC SOI device and the GC SOI device.

Refractive Index Measurement Using SOI Photodiode with SP Antenna toward SOI CMOS-Compatible Integrated Optical Biosensor.

This paper proposes a new optical biosensor composed of a silicon-on-insulator (SOI) p-n junction photodiode (PD) with a surface plasmon (SP) antenna. When the phase-matching condition between two lateral wavelengths of the diffracted light from the SP antenna and the waveguiding mode in the SOI PD is satisfied, we observe sharp peaks in the spectroscopic light sensitivity. Since the peak wavelength depends on the RI change around the SP antenna corresponding to the phase-matching condition, the SOI PDs with an SP antenna can be applied to the optical biosensor. The RI detection limit is evaluated in the measurements with bulk solutions, and 1.11 × 10-5 RIU (refractive index unit) can be obtained, which is comparable to that of a surface plasmon resonance (SPR) sensor, which is well known as a representative optical biosensor. In addition, the response for intermolecular bonds is estimated by the electromagnetic simulations using the finite-difference time-domain (FDTD) method to clarify its ability to detect biomolecular interactions. The results of this paper will provide new ground for high-throughput label-free biosensing, since a large number of SOI PDs with an SP antenna can be easily integrated on a single chip via an SOI complementary metal-oxide-semiconductor (CMOS) fabrication process.

Tunable slow and fast light in a silicon-on-insulator Fano resonator.

Tunable slow and fast light generation in a silicon-on-insulator (SOI) Fano resonator is proposed and experimentally demonstrated. The slow and fast light generation with symmetric and asymmetric coupling conditions of the Fano resonator is theoretically analyzed. Under a slightly imbalanced coupling condition, the two output ports of the Fano resonator could produce a fast light and a slow light, respectively. By utilizing the thermo-optic (TO) effect to change the phase difference of the two optical beams coupled into the resonator, the transition of fast and slow light can be realized at the fixed resonance wavelength. Experimental results show that a slow-to-fast transition (group delay from 0.852 to -1.057 ns) at one resonance wavelength, and a fast-to-slow transition (group delay from -0.22 to 0.867 ns) at another resonance wavelength are realized simultaneously by controlling the microheater to tune the phase difference.

Fabrication technology of void embedded silicon-on-insulator substrate

Void embedded silicon-on-insulator (VESOI) substrate is a newly developed silicon-on-insulator (SOI) substrate for advanced complementary metal oxide semiconductor (CMOS) devices and integration technology. However, in the ion-cutting process for preparing the substrate, numerous hydrogen bubbles aggregate at the cut interface, which compresses the cavity structure and might cause the thin film above the cavity to be damaged and delaminated. Therefore, it is necessary to conduct in-depth research on the stress mechanism and process stability in the preparation of VESOI substrates. This study focuses on a single rectangular cavity structure and uses the fixed-supported beam theory to analyze its mechanical behavior during fabrication, and a three-dimensional model of cavity structure is constructed by using the finite element analysis tool. Through stress simulation, the failure mechanism of the cavity structure is identified, and the weak points are confirmed. The results show that the short side length (&lt;i&gt;w&lt;/i&gt;), top silicon film thickness (&lt;i&gt;t&lt;/i&gt;), and hydrogen bubble pressure are the main factors affecting the stress state of the top silicon film. When the &lt;i&gt;w&lt;/i&gt;/&lt;i&gt;t&lt;/i&gt; ratio exceeds 4–5, the silicon film will fracture owing to excessive tensile stress, and the fracture site is along the long side of the rectangular cavity. By increasing the thickness of the top silicon film slightly and adding support structures inside the cavity (to reduce &lt;i&gt;w&lt;/i&gt;), this work successfully prepares high-quality 8-inch VESOI substrates that meet the requirements for the CMOS production line. The present study is expected to provide valuable idea for the development of integrated technologies relying on VESOI substrates.

On the design of piezoelectric MEMS scanning mirror for large reflection area and wide scan angle

This study designs and implements the piezoelectric MEMS scanning mirror with large scan angle and reflection area for light beam manipulating applications. In this design, the scanning mirror has a large mirror plate (3 mm in diameter) supported by two T-shape torsional springs. The U-shape piezoelectric cantilever acts as the actuator to drive the scanning mirror through the transmission spring. The analytical model is established to provide the design guideline of transmission spring to increase the scan angle. In application, the proposed designs are fabricated on the SOI (silicon on insulator) wafer deposited with the PZT film. Measurements indicate the fabricated mirror could reach an optical scan angle of 140-degree (mechanical scan angle of ±35-degree) when driving at its resonant frequency of 1.5 kHz with a unipolar driving voltage of 42 V. Moreover, no vacuum environment is required for the presented scanning mirror to achieve the above scan angle. This is an extremely large optical scan angle for the MEMS scanner with a mirror plate of 3 mm in diameter. In addition, another U-shape piezoelectric cantilever serves as the position sensor to detect the scan angle of mirror plate. The sensing signals show good linearity with the scan angles and can be exploited as the feedback control. Measurements also demonstrate that the micro scanner could withstand 1500 g shock loading, and the deviation of scan angle is less than 10% after the cycling test under 10 V pp resonant driving in 95%RH and room temperature for 0.2 billion cycles.

Pulsed heterodyne interferometry for nonlinear SOI waveguide characterization

Silicon waveguides are a promising candidate for integrated nonlinear optics applications. Nonlinear coefficients of Silicon on Insulator (SOI) waveguides have been previously measured using techniques such as Z-scan, D-scan, Four Wave Mixing (FWM) and Self-phase modulation. However, they have several drawbacks such as they operate at high power or are cumbersome to setup and require multiple measurements to determine all the coefficients. In this work, we develop a direct and single measurement technique to characterize the nonlinear processes in SOI waveguides. This is achieved by employing a heterodyne interferometric technique to accurately measure minute nonlinear response. The measured nonlinear amplitude and phase shifts are fit to extract third-order nonlinear coefficients of Two-photon absorption, Kerr nonlinear index, Free carrier absorption and Free carrier dispersion. The obtained coefficients for SOI waveguides are close to that found in literature measured using the above-mentioned techniques. The advantages of this method include easy interpretation of the output signal and relatively low power of operation. It is especially advantageous for studying materials such as Phase Change Materials (PCM) in which phase changes occur dynamically. This aspect is quite promising for characterizing emerging materials for integrated photonics applications.

Research progress of intelligent design of on-chip optical interconnection devices

&lt;sec&gt;Compared with traditional communication technologies such as electrical interconnection, optical interconnection technology has the advantages of large bandwidth, low energy consumption, anti-interference, etc. Therefore, optical interconnection is becoming an important approach and development trend of short distance and very short distance data terminal communication. As the chip level optical interconnection is implemented, silicon on insulator (SOI) based on-chip optical interconnection has been widely utilized with the support of a series of multiplexing technologies. In recent decades, many on-chip optical interconnection devices have been developed by using conventional design methods such as coupled-mode, multimode interference, and transmission line theories. However, when used in device design, these conventional methods often face the problems such as complex theoretical calculations and high labor costs. Many of the designed devices also encounter the problems of insufficient compactness and integration, and single function.&lt;/sec&gt;&lt;sec&gt;Intelligent design method has the advantages such as pellucid principle, high freedom of optimization, and good material compatibility, which can solve the problems of conventional design methods to a large extent. With the widespread use of intelligent design methods in the design of on-chip optical interconnection devices, three main trends have emerged. Firstly, the size of on-chip optical interconnect device is gradually developing towards ultra compact size. Secondly, the number of intelligently designed controllable on-chip optical interconnect devices is increasing. Thirdly, on-chip optical interconnect devices are gradually developing towards integration and systematization. This paper summarizes the most commonly used intelligent design methods of photonic devices, including intelligent algorithms based intelligent design methods and neural networks based intelligent design methods. Then, the above three important research advances and trends of intelligently designed on-chip optical interconnection devices are analyzed in detail. At the same time, the applications of phase change materials in the design of controllable photonic devices are also reviewed. Finally, the future development of intelligently designed on-chip optical interconnection devices is discussed.&lt;/sec&gt;

Anneal Behavior of Total Ionizing Dose Irradiated UTBB FD-SOI n-MOSFETs Activated by Hot Carrier Stress

In this article, anneal behavior of total ionizing dose (TID) irradiated ultrathin body and buried oxide fully depleted silicon-on-insulator (UTBB FD-SOI) n-MOSFETs activated by hot carrier stress is observed and discussed. Hot carrier experiments applied on TID irradiated and unirradiated devices show that TID-induced positive oxide charges in buried oxide (BOX) can be neutralized by channel hot electrons, while no additional charged traps are generated. By considering the interactions of charged oxygen vacancies and channel hot electrons, the tunneling anneal process assisted by multiphonon emission is proposed.