Silicon-on-insulator Technology Research Articles

Junctionless accumulation-mode SOI ferroelectric FinFET for synaptic weights

In this work, a novel silicon-on-insulator (SOI) based junctionless-accumulation-mode (JAM) ferroelectric (FE) fin field effect transistor (FinFET) is proposed along with its fabrication process flow at a 3-nm node for synaptic weights. The proposed JAM FE FinFET device can be easily integrated with the fabrication flow of p-FinFET in SOI process flow. The proposed device can be easily incorporated into standard FinFET SOI technology and thus is very attractive with respect to previously proposed devices. Further, using a well-calibrated 3D TCAD simulation setup, we show that the device effectively replicates the behavior required for neuromorphic computing applications. The outcomes of the proposed study emphasize the significance of using the JAM FE FinFET as a synaptic weight device that exhibits a 76 % higher nonvolatile conductance range in the ON-state over existing junctionless and conventional FE FinFET devices. Our simulations show that the proposed device offers continuous linear conductance variation and symmetric switching characteristics, which are essential for neuromorphic applications.

Multimodule microwave assembly for fast readout and charge-noise characterization of silicon quantum dots

Fast measurements of quantum devices is useful in areas such as quantum sensing, quantum computing, and nanodevice quality analysis. Here, we develop a superconductor-semiconductor multimodule microwave assembly to demonstrate charge-state readout at the state of the art. The assembly consist of a superconducting readout resonator interfaced to a silicon-on-insulator (SOI) chiplet containing quantum dots (QDs) in a high-κ nanowire transistor. The superconducting chiplet contains resonant and coupling elements as well as LC filters that, when interfaced with the silicon chip, result in a resonant frequency f=2.12 GHz, a loaded quality factor Q=850, and a resonator impedance Z=470Ω. Combined with the large gate lever arms of SOI technology, we achieve a minimum integration time for single and double QD transitions of 2.77 and 13.5 ns, respectively. We utilize the assembly to measure charge noise over 9 decades of frequency up to 500 kHz and find a 1/f dependence across the whole frequency spectrum as well as a charge-noise level of 4μeV/Hz at 1 Hz. The modular microwave circuitry presented here can be directly utilized in conjunction with other quantum devices to improve the readout performance as well as enable large bandwidth noise spectroscopy, all without the complexity of superconductor-semiconductor monolithic fabrication. Published by the American Physical Society 2024

Design and Development of a MOEMS Accelerometer Using SOI Technology.

The micro-electromechanical system (MEMS) sensors are suitable devices for vibrational analysis in complex systems. The Fabry-Pérot interferometer (FPI) is used due to its high sensitivity and immunity to electromagnetic interference (EMI). Here, we present the design, fabrication, and characterization of a silicon-on-insulator (SOI) MEMS device, which is embedded in a metallic package and connected to an optical fiber. This integrated micro-opto-electro-mechanical system (MOEMS) sensor contains a mass structure and handle layers coupled with four designed springs built on the device layer. An optical reading system using an FPI is used for displacement interrogation with a demodulation technique implemented in LabVIEW®. The results indicate that our designed MOEMS sensor exhibits a main resonant frequency of 1274 Hz with damping ratio of 0.0173 under running conditions up to 7 g, in agreement with the analytical model. Our experimental findings show that our designed and fabricated MOEMS sensor has the potential for engineering application to monitor vibrations under high-electromagnetic environmental conditions.

A Small-Scale, Rat-Inspired Whisker Sensor for the Perception of a Biomimetic Robot: Design, Fabrication, Modeling, and Experimental Characterization

In this article, we present a rat-inspired whisker sensor for a biomimetic robotic rat and demonstrate its superior tactile perception performance. In particular, the design, fabrication, modeling, and experimental characterization are presented. The sensor is fabricated using silicon-on-insulator (SOI) technology. Moreover, by modeling the whisker as a Euler–Bernoulli beam (EBB) using a support vector machine (SVM) algorithm, we develop the sensor’s capability to identify object features. An experimental evaluation demonstrates the sensor’s outstanding texture discrimination ability (with an accuracy of 88.3%) and excellent performance on contour reconstruction [with a 97.14% goodness of fit (GOF)]. In addition, by realizing the robotic rat’s wall-following motion using the whisker sensor, many more features of a wall can be obtained with high accuracy. As a result, this work is, to the best of our knowledge, the first to achieve experimental progress in using a whisker sensor to control a small-scale robot on the order of a few tens of centimeters. Moreover, the whisker sensor extends this off-the-shelf SOI technology from micro to macro environments, giving it the potential for use in other miniature robots for tactile perception.

Germanium Quantum Wells for Non-Linear Integrated Photonics

In recent years, mid-infrared integrated photonics has raised an increasing interest due to the envisioned applications in molecular sensing, environmental monitoring and security. The Silicon-on-insulator (SOI) based technology, operating at wavelengths λ < 3.2 μm has already reached a significant technology readiness level. By leveraging the maturity of the SOI technology and taking advantage of the high index contrast between Si and SiO2 many functionalities such as low loss waveguiding, modulation and frequency comb generation have already been demonstrated. However, the wavelength range is limited by the absorption of the SiO2 layer. Many material platforms, such as III-V semiconductors, halides and chalcogenides are under investigation to fill this gap. Of particular interest is the Ge-rich SiGe-on-Si material platform, thanks to its compatibility to already existing foundry processes and its wide transparency at the wavelengths of interest. Nevertheless, key functionalities such as wavelength conversion, photodetection and high-speed modulation are still missing.A viable way to achieve such advanced functionalities is the exploitation of intersubband transitions (ISBTs) in hole-doped Ge/SiGe quantum wells (QWs). In particular, ISBTs in can be leveraged to engineer an artificial second-order optical nonlinearity in group IV materials, where it is normally absent for symmetry reasons. In this work, we exploit ISBTs in asymmetric coupled Ge/SiGe (ACQWs) (see Fig.1) to achieve highly efficient second harmonic generation at mid-infrared frequencies. The ACQW has been designed with an advanced semi-empirical first neighbor sp3d5s* tight-binding model, which has been used to calculate the second-order nonlinear susceptibility χ(2) (see fig 1b).The ACQW has been then grown by Low-Energy Plasma-Enhanced Chemical Vapor Deposition (LEPECVD) and structurally characterized by x-ray diffraction (XRD) and high-resolution scanning transmission electron microscopy (STEM) . For the optical measurements, samples were cut in a 2 mm single-pass surface-plasmon waveguide with the side facets shaped to 70° with respect to the growth plane and the top facet close to the ACQWs region coated by a Ti/Au layer. Then the samples (cooled at 10 K) have been pumped with a CW quantum cascade laser emitting at λ =10.3 μm. The light coming out from the samples have been then filtered and collected by an MCT detector. The second harmonic emission has been recorded as a function of the input power (see fig. 1c) and a c(2) = 6x104 pm/V has been extracted from the measurement, a two orders of magnitude improvement with respect to the best nonlinear crystals.Finally, the possibility to integrate ACQWs in waveguides has been theoretically investigated. Since artificial nonlinearities based on ISBTs involve real quantum states, as opposite to the virtual quantum states employed in standard nonlinear crystals, significative optical absorption at the pump and at the second harmonic wavelengths must be considered. Therefore, the length of the ACQW waveguide must be carefully designed in order to limit the optical losses. By solving the coupled wave equations with optical absorption at the pump and second harmonic wavelengths, we show that high conversion efficiencies around ≈ 10% can be achieved with waveguide integrated ACQWs for an optimal waveguide length of a ≈200 μm.The integration scheme, shown in fig 2a, consists in a stack of ACQW integrated in a waveguide containing a periodic corrugation, which is necessary to achieve quasi-phase matching between the pump and the second harmonic. Input and output coupling of the light is achieved through adiabatic tapers by integrating the ACQW stack on a Si0.3Ge0.7 waveguide, where the light is injected and from which it is collected and measured. The pump and the second harmonic mode are fairly overlapped in the ACQW region, as shown in fig 2b and 2c, where the distribution of the first TM mode has been simulated using the Lumerical software package.In conclusion, Ge/SiGe ACQW are very promising to expand the functionalities available in MIR integrated photonic circuits, especially in the important spectral region up to 10 μm. In particular, the experimental data obtained from the material characterization, as well as the preliminary studies of waveguide integration show that Ge/SiGe ACQW has the potential to realize highly efficient integrated wavelength converters.Acknowledgments: This work has been supported by Fondazione Cariplo, grant n° 2020-4427. Figure 1

Fully Depleted SOI Technology for Millimeter-Wave Integrated Circuits

Performances of high-frequency integrated circuits are directly linked to the analog and high frequency characteristics of the transistors, the quality of the back-end of line process as well as the electromagnetic properties of the substrate. Today, Partially Depleted Silicon-on-Insulator (SOI) MOSFET is the mainstream technology for RF SOI systems. Fully Depleted (FD) SOI MOSFET is foreseen as one of the most promising candidates for the development of future lower power wireless communication systems operating in the millimeter-wave range. The high frequency performances of FD SOI transistors are presented at room but also at cryogenic and high temperature. Recently published results for FD SOI switches and low noise amplifiers are summarized. And finally, the potential interest and challenges to move from standard to high resistivity FD SOI substrates are discussed.

Body Current Optimization using Threshold-Voltage-Adjust-Implant Engineering in 45nm SOI MOSFET

In this paper, for the first time, Threshold-voltage-adjust-implant is engineered to optimize body current in 45 nm Silicon-on-Insulator (SOI) MOSFET. The peak value and peak position concentration of the Gaussian implant under the gate oxide in the silicon body are varied in order to optimize the body current in SOI technology. The variations affect the devices’ threshold voltages. In order to make a fair comparison, the gate work function is changed to obtain the same threshold voltage within the entire simulated devices and operating regime. The body current is monitored while the it is swept from 0 V to 1.5 V. The maximum of the body current is observed at VDS=1.5 V. The concentration of Threshold-voltage-adjust-implant peak value is changed from 1.7E17 cm-3 to 7E18 cm-3. The peak position of the implant is varied from 0 nm right under the gate oxide to 20 nm below the gate oxide and silicon surface. It is observed that the body current is minimized at the peak value concentration of 7E17 cm-3 and peak position of 0 nm. This can happen by proper choice of the gate work function and gate material. The minimization of body current leads to the less requirement for body contacts and smaller gate parasitic capacitance which, in turn, concludes higher operating frequency and larger fT.

Measurement and Evaluation of the Within-Wafer TID Response Variability on BOX Layer of SOI Technology

Within-wafer total ionizing dose (TID) response variability on buried oxide (BOX) layer of silicon-on-insulator (SOI) technology is investigated in this article. TID response variability is measured by the threshold voltage and OFF-state leakage of transistors evenly distributed on the wafer locations. Experimental results show the larger standard deviation of threshold voltage and OFF-state leakage distribution for irradiated devices than unirradiated devices, illustrating the within-wafer TID response variability. The hole traps variation in the BOX layer is responsible for the within-wafer TID response variability of SOI technology. Moreover, a data analysis method according to T-distribution is proposed to obtain the within-wafer TID response variability by the sampling testing results of limited wafer locations. Our data show that the T-distribution method is reasonable to assess the TID-induced variability of a process when only a few samples are available.

Robust Pressure Sensor in SOI Technology with Butterfly Wiring for Airfoil Integration.

Current research in the field of aviation considers actively controlled high-lift structures for future civil airplanes. Therefore, pressure data must be acquired from the airfoil surface without influencing the flow due to sensor application. For experiments in the wind and water tunnel, as well as for the actual application, the requirements for the quality of the airfoil surface are demanding. Consequently, a new class of sensors is required, which can be flush-integrated into the airfoil surface, may be used under wet conditions—even under water—and should withstand the harsh environment of a high-lift scenario. A new miniature silicon on insulator (SOI)-based MEMS pressure sensor, which allows integration into airfoils in a flip-chip configuration, is presented. An internal, highly doped silicon wiring with “butterfly” geometry combined with through glass via (TGV) technology enables a watertight and application-suitable chip-scale-package (CSP). The chips were produced by reliable batch microfabrication including femtosecond laser processes at the wafer-level. Sensor characterization demonstrates a high resolution of 38 mVV−1 bar−1. The stepless ultra-smooth and electrically passivated sensor surface can be coated with thin surface protection layers to further enhance robustness against harsh environments. Accordingly, protective coatings of amorphous hydrogenated silicon nitride (a-SiN:H) and amorphous hydrogenated silicon carbide (a-SiC:H) were investigated in experiments simulating environments with high-velocity impacting particles. Topographic damage quantification demonstrates the superior robustness of a-SiC:H coatings and validates their applicability to future sensors.

Proton radiation hardness of x-ray SOI pixel sensors with pinned depleted diode structure

X-ray silicon-on-insulator (SOI) pixel sensors, “XRPIX,” are being developed for the next-generation x-ray astronomical satellite, “FORCE.” The XRPIX is fabricated with the SOI technology, which makes it possible to integrate a high-resistivity Si sensor and a low-resistivity Si complementary metal oxide semiconductor (CMOS) circuit. The CMOS circuit in each pixel is equipped with a trigger function, allowing us to read out outputs only from the pixels with x-ray signals at the timing of x-ray detection. This function thus realizes high throughput and high time resolution, which enables to employ anti-coincidence technique for background rejection. A new series of XRPIX named XRPIX6E developed with a pinned depleted diode (PDD) structure improves spectral performance by suppressing the interference between the sensor and circuit layers. When semiconductor x-ray sensors are used in space, their spectral performance is generally degraded owing to the radiation damage caused by high-energy protons. Therefore, before using an XRPIX in space, it is necessary to evaluate the extent of degradation of its spectral performance by radiation damage. Thus, we performed a proton irradiation experiment for XRPIX6E for the first time at Heavy Ion Medical Accelerator in Chiba in the National Institute of Radiological Sciences. We irradiated XRPIX6E with high-energy protons with a total dose of up to 40 krad, equivalent to 400 years of irradiation in orbit. The 40-krad irradiation degraded the energy resolution of XRPIX6E by 25 ± 3 % , yielding an energy resolution of 260.1 ± 5.6 eV at the full-width half maximum for 5.9 keV X-rays. However, the value satisfies the requirement for FORCE, 300 eV at 6 keV, even after the irradiation. It was also found that the PDD XRPIX has enhanced radiation hardness compared to previous XRPIX devices. In addition, we investigated the degradation of the energy resolution; it was shown that the degradation would be due to increasing energy-independent components, e.g., readout noise.

An ESD-Protected, One-Time Programmable Memory Front-End Circuit for High-Voltage, Silicon-on-Insulator Technology

An electrostatic discharge (ESD)-protected one-time-programmable (OTP) memory front-end circuit, for high-voltage (HV) applications, designed and manufactured in silicon-on-insulator (SOI) technology, is presented. The SOI technology meets HV functional-isolation and level-shifting requirements but is not suitable for advanced analog circuits. The presented OTP memory is discussed as an introduction to digital programmability in the considered technology. The memory element consists of an antifuse type structure and is implemented using a 5-V nMOS with L=1 μm and W=1.2 μm. The cell memory allows for significant area and power savings in the adopted HV technology. Conditions for this require that an efficient ESD protection will guarantee safe operation, even in the presence of a small and fragile on-chip element whose undesired burning would compromise the programming mechanism, and consequently the reliability, of the circuit. Details about the circuit design implementation of the front-end circuit for both read and write circuits and ESD protection are described with experimental results validating the proposed implementation.

High spatial resolution monolithic pixel detector in SOI technology

This paper presents test-beam results of monolithic pixel detector prototypes fabricated in 200 nm Silicon-On-Insulator (SOI) CMOS technology studied in the context of high spatial resolution performance. The tested detectors were fabricated on a 500 μm thick high-resistivity Floating Zone type n (FZ-n) wafer and on a 300 μm Double SOI Czochralski type p (DSOI Cz-p) wafer. The pixel size is 30 μm×30 μm and two different front-end electronics architectures were tested, a source follower and a charge-sensitive preamplifier. The test-beam data analyses were focused mainly on determination of the spatial resolution and the hit detection efficiency. In this work different cluster formation and position reconstruction methods are studied. In particular, a generalization of the standard η-correction adapted for arbitrary cluster sizes, is introduced. The obtained results give in the best case a spatial resolution of about 1.5 μm for the FZ-n wafer and about 3.0 μm for the DSOI Cz-p wafer, both detectors showing detection efficiency above 99.5%.

Gate Oxide Thickness Influence on the Gate Induced Floating Body Effect in SOI Technology

In this work, we explore the gate oxide thickness influence on the Gate Induced Floating Body effect (GIFBE). This study was performed through two-dimensional numerical simulations and electrical measurements. The available devices are from 130nm and 65nm Silicon-On-Insulator (SOI) MOSFET technologies. The GIFBE and threshold voltage are evaluated as function of the gate oxide thickness reduction and an overlap tendency of the first and the second transconductance peaks is observed.

Sigma-Delta ADC on SOI Technology for Working at High Temperatures

We consider the integrated circuit design and the measurement results of test crystals for the 12-bit sigma-delta analog-to-digital converter (ADC) based on 180 nm silicon-on-insulator (SOI) technology from X-FAB. The ADC processes input signals in the frequency range up to 100 kHz in the temperature range of –40…+175 °C with the supply voltage equal to 3.3 V and the modulator clock frequency equal to 10 MHz. The circuit consists of the 5-th order switched-capacitor low-pass pre-filter to limit the input signal spectrum, the cascade connection of the second order sigma-delta modulators, and the digital decimation filter to reduce the clock frequency by 48 times. The main blocks of cutoff filter and modulator are assembled according to the balanced scheme on integrators based on operational transconductance amplifiers with the unity gain bandwidth of 63 MHz. The dynamic element matching circuit is used to expand the dynamic range of converter. It reduces the level of nonlinear distortions in digital-to-analog converters in the feedback circuits of modulator. The value of the SINAD parameter is not worse than 68 dB for converting the signal with the differential amplitude equal to 500 mV at the frequency of 100 kHz.

Deep-Depletion Effect in SOI Substrates and its Application in Photodetectors With Tunable Responsivity and Detection Range

We present an interesting transient effect found in silicon-on-insulator (SOI) transistors, where the drain current responds slowly to a back-gate voltage ( ${V}_{\text {BG}}$ ) pulse. This transient mechanism is due to the deep-depletion region in the SOI substrate induced by the ${V}_{\text {BG}}$ pulse and has been validated by experimental and TCAD simulation results. The deep-depletion characteristic can be employed for photodetection in a fully depleted (FD)-SOI MOSFET device. We have measured the photoresponse of the FD-SOI MOSFET under various light illumination conditions and studied systematically the impact of the ${V}_{\text {BG}}$ pulse duty ratio, amplitude, and period on the responsivity and detection range. An optimized device structure, fabricated in an advanced ultrathin body and buried oxide (BOX) (UTBB) SOI technology, shows low operation voltage and extended detection range.

Development of circuit integrated monolithic SOI-SiPM for radiation detection

A prototype of the 250-μm pitch 8 × 8 silicon photomultiplier (SiPM) array was designed and fabricated by the 0.2 μm 5-metal Silicon on Insulator (SOI)-CMOS technology aiming at the monolithic integration of sensors and front-end electronics. The SOI technology enables the 3D integration of electronics without a mechanical bonding that allows the pixel size refinement, the backside illumination, and the improved electronics performance. The signal of SiPM is processed by the front-end electronics, which consists of a preamplifier, a shaper, and four discriminators. The design modification to sensors and the performance evaluations of the sensors and front-end electronics are reported in this paper.

Synthesis and transport properties of FET based on Heusler alloy thin films formed by rapid thermal annealing

In this work we show a preparation technique of Co2FeSi full-Heusler alloy thin films on silicon-on-insulator (SOI) substrates, employing rapid thermal annealing (RTA). The films of the Co2FeSi alloy were formed by a silicidation reaction, caused by RTA, between the ultrathin SOI (001) layer and the Fe/Co layers deposited on it. It is assumed that this technology is compatible with the process of formation of a half-metal source-drain in an advanced CMOS and SOI technology and will be applicable for the manufacture of a source-drain of a field-effect transistor. Schottky barrier field-effect transistors (FET) with a back-gate, based on silicon nanowires with source and drain of a Co2FeSi film, synthesized on an SOI substrate, were manufactured. The transport properties of the device were investigated.

Understanding the Difference in Soft-Error Sensitivity of Back-Biased Thin-BOX SOI SRAMs to Space and Terrestrial Radiation

High tolerance against soft errors is regarded as one of the advantages of silicon-on-insulator (SOI) technology, as well as the reduction in power consumption by applying a back-bias from under the buried oxide layer (BOX). These advantages are appealing to Internet-of-Things (IoT) and space applications. Recently, it was found in a heavy-ion experiment that a static random-access memory (SRAM) fabricated with a 65-nm thin-BOX SOI technology exhibited a 100-fold soft-error sensitivity when it received a back-bias. This was due to long line-type formations of multiple cell upsets (MCUs) caused by radiation-induced potential perturbation under the BOX. However, devices fabricated with a similar technology tested with terrestrial neutrons did not show such a phenomenon in another previous study. To understand this difference, in the present work, a resistance-based model is adopted. Prediction of device soft-error sensitivity due to line-type MCUs under different radiation environment are also made. Then, characteristics of secondary ions generated by terrestrial neutrons in silicon devices are studied using simulation.

A High Linearity +44.5-dBm IP $3~C$ -Band 6-Bit Digital Phase Shifter Using SOI Technology for Phased Array Applications

A 6-bit digital phase shifter in 0.18- $\mu \text{m}$ silicon-on-insulator (SOI) process is presented. It operates over a 4–7-GHz frequency band and provides 360° of phase coverage with 5.625° resolution using 64 phase states. The SOI phase shifter has a compact size of $1320\,\,\mu \text{m}\,\,\times 780\,\,\mu \text{m}$ . Compared to a state-of-the-art 0.15- $\mu \text{m}$ pHEMT-based product design, the SOI IC design is five times smaller in size with 2–6 dB higher IP3 and power handling capability. To the best of authors’ knowledge, this is the highest IP3 of phase shifter using commercial SOI technology. These SOI monolithic microwave integrated circuit (MMIC) phase shifter characteristics are attractive for military radar and commercial phased array communication systems where cost, size, weight, and power (C-SWAP) and high linearity are required.

Comparison of the Total Dose Responses of Fully Depleted SOI nMOSFETs With Different Geometries for the Worst Case Bias Conditions

Fully depleted (FD) silicon-on-insulator (SOI) nMOSFETs fabricated using 0.2- $\mu \text{m}$ SOI technology with external body contact (EBC) and floating body (FB) structures are irradiated up to 500 krad(Si) using 60Co gamma rays under the transmission gate (TG) and OFF bias conditions, respectively. The threshold voltage shift of the back transistors due to radiation-induced charge trapping in the buried oxide (BOX) is used to characterize the total dose response of irradiated back transistors. The results indicate that, overall, the TG biased EBC transistors with various gate lengths are more sensitive to the total dose radiation than the OFF biased FB counterparts at low dose levels. Furthermore, for the shorter gate transistors with a supply voltage of 1.8 V, a relatively complex correlation exists between the total dose response and the gate length. In particular, the back transistor of the TG biased 0.20- $\mu \text{m}$ 1.8-V EBC transistor reveals smaller threshold voltage shifts than the OFF biased counterpart at approximately 500 krad(Si) because of the saturation of its threshold shift with increased doses, and a similar radiation response is observed for the TG biased 0.35- $\mu \text{m}$ EBC transistor with a supply voltage of 2.5 V. We found that the 2.5-V back transistors exhibited greater radiation hardness than the 1.8-V counterparts with the same bias configuration in most cases.