Silicon-on-insulator Metal–semiconductor Field-effect Transistor Research Articles

Improved SOI-MESFET structures for enhanced efficiency and optimized DC/RF characteristics

ABSTRACT In this paper, two new silicon on insulator metal-semiconductor field effect transistor (SOI-MESFET) structures are presented. Two parallel layers of oxide and aluminium are added at the gate edge of these structures. Also, in the buried oxide part of the Aluminium Edge and Silicon-Well MESFET (AESW-MESFET) structure, a silicon well and two aluminium layers are added. Moreover, and to improve the DC and RF characteristics, as compared to the Conventional MESFET (C-MESFET) structure, a silicon well and a silicon layer are added in the box oxide section in the Silicon Edge and Silicon-Well MESFET (SESW-MESFET) structure. By these changes, the value of the breakdown voltage in the normal structure has increased from 15.8 V to 33.1 V and 30.9 V in the proposed AESW-MESFET and SESW-MESFET structures, respectively. In addition, the maximum output power has been associated with a significant increase of 4.44 and 5.24 times, respectively. Compared to the C-MESFET, the proposed structures reduce gate-source and gate-drain capacitors and significantly increases conductivity. The cut-off frequency values are increased from 19.3 GHz (the normal structure) to 37.3 GHz and 35 GHz (the proposed structures), and the maximum oscillation frequencies are increased from 80 GHz to 154 GHz and 102.3 GHz. Therefore, the results show that the proposed structures have good performance and the ability to work at high power and high frequency.

An impressive structure containing triple trenches for RF power performance (TT-SOI-MESFET)

The radio-frequency (RF) power characteristics of a silicon-on-insulator metal–semiconductor field-effect transistor (SOI-MESFET) were improved with effective optimization of the simple structure. Separate triple trenches were introduced in the proposed device to improve the electrical performance. The SOI-MESFET with separate triple trenches (TT-SOI-MESFET) benefits from these trenches for dispersion of the potential lines, leading to enhanced RF power features. A comparison of the proposed structure with the simple SOI-MESFET structure revealed that the TT-SOI-MESFET exhibited improved RF power characteristics in terms of breakdown voltage, drain–source conductance, gate–source capacitance, total gate capacitance, maximum output power density, minimum noise figure and global lattice temperature.

Successfully Controlled Potential Distribution in a Novel High-Voltage and High-Frequency SOI MESFET

Potential distribution of a silicon-on-insulator metal-semiconductor field effect transistor (SOI-MESFET) is successfully controlled by introducing a new structure. The structure we established, utilizes a P-type layer embedded in the drift region. Also, the doping engineering is applied to the proposed structure in order to more enhance the performance superiority of the novel structure called SPL-DE SOI MESFET. The P-type layer and doping engineering control the potential distribution and help the proposed structure to improve the important parameters, such as breakdown voltage, driving current, power gains, oscillation frequency, transconductance, maximum output power density, and gate-drain parasitic capacitance. As a result, the SPL-DE SOI MESFET has superior electrical performances in comparison with the similar device based on the conventional structure thus taking into account the special considerations for the high-voltage and high-frequency applications.

A novel high-performance high-frequency SOI MESFET by the damped electric field

In this paper, we introduce a novel silicon-on-insulator (SOI) metal-semiconductor field-effect-transistor (MESFET) using the damped electric field (DEF). The proposed structure is geometrically symmetric and compatible with common SOI CMOS fabrication processes. It has two additional oxide regions under the side gates in order to improve DC and RF characteristics of the DEF structure due to changes in the electrical potential, the electrical field distributions, and rearrangement of the charge carriers. Improvement of device performance is investigated by two-dimensional and two-carrier simulation of fundamental parameters such as breakdown voltage (VBR), drain current (ID), output power density (Pmax), transconductance (gm), gate–drain and gate–source capacitances, cut-off frequency (fT), unilateral power gain (U), current gain (h21), maximum available gain (MAG), and minimum noise figure (Fmin). The results show that proposed structure operates with higher performances in comparison with the similar conventional SOI structure.

A Novel MESFET structure by U-shape buried oxide for improving the DC and RF Characteristics

For the first time, a new type of silicon on insulator metal semiconductor field-effect transistor (SOI-MESFET), the U-shape buried oxide (UBO) SOI-MESFET, is proposed and investigated. The proposed structure is similar to that of the conventional SOI-MESFET with the exception that the shape of buried oxide is reformed to the U-shape. The influence of U-shape buried oxide on saturation current (ID), breakdown voltage (VBR), and small-signal characteristics of the UBO-SOI MESFET is studied by numerical device simulation and compared with a conventional SOI MESFET (C-SOI MESFET) characteristics. The simulated results show that the U-shape buried oxide has excellent effect on cut-off frequency (fT), maximum oscillation frequency (fmax), maximum available gain (MAG), and unilateral power gain (U) for the UBO-SOI MESFET structure. Also the U-shape buried oxide leads to the enhancement of VBR and ID of the UBO-SOI MESFET structure. The optimized results showed that VBR of the UBO-SOI MESFET is 77% larger than that of the C-SOI MESFET, which meanwhile maintains almost 90% higher saturation drain current characteristics. The maximum output power densities of 0.05 and 0.014W/mm are obtained for the UBO-SOI and C- SOI MESFET structures, respectively, which means about 3.5 times larger output power for the proposed device.

Simulation analysis of a novel dual-trench structure for a high power silicon-on-insulator metal–semiconductor field effect transistor

In this paper, a silicon-on-insulator (SOI) metal–semiconductor field-effect transistor (MESFET) by a novel dual-trench technique is presented. In the proposed technique, the dual-trench is created in the buried oxide and filled with p-type and n-type doped Si. The p-type trench beneath the source increases breakdown voltage (VBR). Also, the n-type trench beneath the gate improves the drain current (ID). We call this new structure as Dual-Trench SOI MESFET (DT-MESFET). DC and radio frequency (RF) characteristics of the proposed structure are analyzed by 2-D numerical simulation and compared with conventional SOI MESFET (C-MESFET) characteristics. The extracted results show that the dual-trench technique has excellent effect on ID, VBR, and maximum output power density (Pmax) of the device. The parameters, VBR, ID, and Pmax of the DT-MESFET structure are improved by 55.55%, 50%, and 300% compared with those of the C-MESFET structure, respectively. Also, the dual-trench technique leads to the enhancement of maximum oscillation frequency and maximum available gain. Therefore, the novel SOI MESFET structure has superior electrical characteristics as compared to the similar device based on the conventional structure.

A novel SOI MESFET by reducing the electric field crowding for high voltage applications

In this paper, a novel silicon-on-insulator (SOI) metal–semiconductor field-effect transistor (MESFET) is presented by reducing the electric field crowding. The charge distribution in channel modifies by reducing the electric field crowding and results in the breakdown voltage (VBR) improves. To reduce the electric field crowding, a buried field plate (BFP) is employed in the buried oxide of the SOI MESFET and connected to source. DC and frequency response characteristics of the SOI MESFET with BFP (BFP-SOI MESFET) are analyzed via a 2-D numerical simulation and the results are compared with characteristics of a conventional SOI MESFET (C-SOI MESFET) structure. The BFP has outstanding effect on the VBR of the device. The VBR of the proposed BFP-SOI MESFET improves by 84% compared with that of the C-SOI MESFET. Although the saturation drain current of the proposed structure has decreased to a small extent, 37% increase in maximum power density is obtained. In addition, the proposed structure showed an approximately 70% decrease in the gate-drain capacitance (Cgd), which in-turn resulted in 5dB maximum available gain (MAG) improvement at 2GHz. As a result of employing the buried field plate, the BFP SOI-MESFET has an outstanding DC and frequency response performance compared with the C-SOI MESFET.

A novel SOI MESFET by $$\uppi $$ π -shaped gate for improving the driving current

This paper introduces a novel silicon-on-insulator (SOI) metal---semiconductor field-effect transistor (MESFET) with $$\uppi $$ ? -shaped gate with triple workfunction ( $$\uppi $$ ? -SOI MESFET) to improve the DC and radio frequency characteristics. The DC and radio frequency characteristics of the proposed structure are analyzed by 2-D ATLAS international simulator and compared with a conventional SOI MESFET (C-SOI MESFET). The simulated results show that the proposed SOI MESFET has excellent effect on the breakdown voltage and the driving current. The breakdown voltage of the $$\uppi $$ ? -SOI MESFET structure gets 54 % enhancement compared with that of the C-SOI MESFET structure and also the driving current of the $$\uppi $$ ? -SOI MESFET structure gets 66.66 % enhancement compared with that of the C-SOI MESFET structure. Other main characteristics such as maximum output power density, maximum oscillation frequency and maximum available gain have been evaluated and improved in the proposed structure.

A Novel High-Breakdown-Voltage SOI MESFET by Modified Charge Distribution

In this paper, a novel silicon-on-insulator (SOI) metal-semiconductor field-effect transistor (MESFET) with modified charge distribution is presented. Changing charge distribution leads to lower electric field crowding and increased breakdown voltage ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">BR</sub> ). For modifying charge distribution, a metal region (MR) is utilized in buried oxide of the SOI MESFET. In order to achieve the best results, the MR location and dimensions are optimized carefully. DC and radio frequency characteristics of the SOI MESFET with MR (MR-SOI MESFET) are analyzed by 2-D numerical simulation and compared with conventional SOI MESFET (C-SOI MESFET) characteristics. The simulated results show that the MR has excellent effect on the <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">BR</sub> of the device. The <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">BR</sub> of the MR-SOI MESFET structure improves by 116% compared with that of the C-SOI MESFET structure. Although drain current of the proposed structure reduces slightly, 126% improvement in maximum output power density of the device is achieved due to high enhancement of the <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">BR</sub> . Also, the MR leads to the enhancement of maximum oscillation frequency and maximum available gain of the MR-SOI MESFET structure. As a result, the MR-SOI MESFET structure has superior electrical performances in comparison with the similar device based on the conventional structure.

Compact modeling of a PD SOI MESFET for wide temperature designs

A compact model for the partially depleted (PD) silicon-on-insulator (SOI) metal semiconductor field effect transistor (MESFET) is presented. The absence of a gate-oxide makes the SOI MESFET extremely robust, able to withstand high voltages, and useful for extreme environment electronics. These devices have been fabricated using a standard SOI CMOS process. In contrast to SOI MOSFETs and GaAs MESFETs, the source–substrate voltage has a significant impact on the channel current. In this work a model has been developed that includes the effect of the buried oxide on the performance of the MESFET. The model has been verified for a wide temperature range of −180 to 150 °C. A behavioral model has been included to model the breakdown voltage. The core DC and RF models have been adapted from the commercially available Triquint's Own Model (TOM3) MESFET model. Building from the TOM3 model, a measurement-based approach is used to develop a four-terminal compact model using Verilog-A. The charge-based approach, using S-parameter measurements was used to develop the capacitance model. We also present a voltage reference circuit using two MESFET transistors to verify the model and explore wide temperature range circuit applications.

Effect of interface roughness on silicon-on-insulator–metal-semiconductor field-effect transistor mobility and the device low-power high-frequency operation

We have developed a simulation model based on the solution of the Boltzmann transport equation (BTE) for modeling n-channel silicon-on-insulator (SOI) metal-semiconductor field-effect transistor (MESFETs) using the ensemble Monte Carlo device simulation technique. All relevant scattering mechanisms for the silicon material system have been included in the model. In addition to phonon scattering, to properly describe the operation of the SOI MESFET devices, in our theoretical model we have also included surface or interface-roughness scattering. Following Fischetti and Laux[J. Appl. Phys. 89, 1205 (2001)] we first model interface roughness as a real space scattering event, separated into specular and diffusive (isotropic) type of reflection from an ideal atomically flat interface. This model gives rise to low-field silicon electron mobility values in agreement with available experimental data. To further verify our mobility results, we also treat interface roughness as a boundary condition based on the Boltzmann-Fuch method. To examine the performance improvement of this device structure, in contrast to some previous studies, here we have simulated analogous SOI MESFET and SOI MOSFET devices. The results of these investigations suggest that the mobility of the SOI MOSFET device follows the experimental values and the mobility of the SOI MESFET is three to five times higher than that of the SOI MOSFET in the subthreshold and the on-state regime. These high mobility values suggest that this device structure is a promising candidate for low-power high-frequency applications.