Silicon-on-insulator Metal-oxide-semiconductor Field-effect Transistors Research Articles

A Subthreshold Swing Model for Fully-Depleted Silicon-on-Insulator Metal–Oxide–Semiconductor Field Effect Transistors with Vertical Gaussian Profile

A compact subthreshold swing model is proposed for the short-channel fully-depleted (FD) silicon-on-insulator (SOI) metal–oxide–semiconductor field effect transistors (MOSFETs) with vertical Gaussian doping profile in this paper. Considering the channel potential which is influenced by the non-uniform doping profile, the model is derived by using the concept of effective conduction path effect (ECPE). The validity of the proposed model is shown by comparing the calculated results with the Sentaurus technology computer-aided design (TCAD) numerical simulation data. The model is believed to provide a better physical insight and understanding of FD SOI MOSFETs with a non-uniform doping profile operating in the subthreshold regime.

Exact control of junction position using epitaxial NiSi2 crystallization in ultrathin silicon-on-insulator metal-oxide-semiconductor field-effect transistors

This paper reports the demonstration of exact control of the junction position in ultrathin silicon-on-insulator (SOI) metal-oxide-semiconductor field-effect transistors (MOSFETs) using epitaxial NiSi2 crystallization. In the ultrathin SOI (100) plane, NiSi2 first grows in the <100> vertical direction and along the SOI/buried oxide (BOX) interface. Subsequently, NiSi2 grows in the <110> lateral direction and sustains a (111) facet. We found that epitaxial NiSi2 crystallization in ultrathin SOI proceeds first vertically, then laterally, in a step-by-step crystallization pattern. Epitaxial NiSi2 crystallization rates for the (100) and (111) planes are proportional to the root square of the annealing time associated with the lattice diffusion reaction. Thus, the junction position in an ultrathin SOI MOSFET with metal source/drain can be exactly controlled by annealing times.

Investigation of Random Telegraph Signal with PD SOI MOSFETs

A novel method, called random telegraphy signal (RTS), was constructed to characterize the gate oxide quality and reliability of metal-oxide-semiconductor field-effect-transistors (MOSFETs). With the aggressive scaling of device size, drain current RTS (ID-RTS) become a critical role in carrier transport of MOSFETs. Besides, RTS in gate leakage current (I¬G-RTS) was denoted as the other new method to understand property of gate oxide. Recently, the study of RTS has also been made in MOSFETs with metal gate and high dielectric constant (metal gate/high-k). However, the RTS in partial depleted silicon-on-insulator MOSFETs (PD SOI MOSFETs) has not comprehensively been studied yet. This paper investigates RTS characteristics in PD SOI MOSFETs.

Leakage current reduction in nanoscale fully-depleted SOI MOSFETs with modified current mechanism

For the first time, we have presented a novel nanoscale fully depleted silicon-on-insulator metal-oxide-semiconductor field-effect transistor (SOI-MOSFET) with modified current mechanism for leakage current reduction. The key idea in this work is to suppress the leakage current by injected carriers decrement into the channel from the source in weak inversion regime while we have created a built-in electric field in the channel for improving the on current of device. Therefore, we have introduced a trapezoidal doping that distributed vertically in the channel and called the proposed structure as vertical trapezoid doping fully depleted silicon-on-insulator MOSFET (VTD-SOI). Using two-dimensional two-carrier simulation we demonstrate that the VTD-SOI decreases the leakage current in comparison with conventional uniform doping fully depleted silicon-on-insulator MOSFET (C-SOI). Also, our results show short channel effects (SCEs) such as drain induced barrier lowering (DIBL) and threshold voltage roll-off improvement in the proposed structure. Therefore, the VTD-SOI structure shows excellent performance for scaled transistors in comparison with the C-SOI and can be a good candidate for CMOS low power circuits.

A unified charge-based model for SOI MOSFETs applicable from intrinsic to heavily doped channel

A unified charge-based model for fully depleted silicon-on-insulator (SOI) metal-oxide semiconductor field-effect transistors (MOSFETs) is presented. The proposed model is accurate and applicable from intrinsic to heavily doped channels with various structure parameters. The framework starts from the one-dimensional Poisson—Boltzmann equation, and based on the full depletion approximation, an accurate inversion charge density equation is obtained. With the inversion charge density solution, the unified drain current expression is derived, and a unified terminal charge and intrinsic capacitance model is also derived in the quasi-static case. The validity and accuracy of the presented analytic model is proved by numerical simulations.

Gate Length and Gate Width Dependence of Drain Induced Barrier Lowering and Current-Onset Voltage Variability in Bulk and Fully Depleted Silicon-on-Insulator Metal Oxide Semiconductor Field Effect Transistors

This paper presents the statistical analysis of a newly found drain current variability component called “current-onset voltage” (COV) variability as well as drain induced barrier lowering (DIBL) variability in bulk and fully-depleted (FD) silicon-on-insulator (SOI) devices. Intensive variability measurement data show that gate length and gate width dependent COV variability and DIBL variability in bulk metal–oxide–semiconductor field effect transistors (MOSFETs) deviate from the straight line in the Pelgrom plot. On the other hand, COV variability and DIBL variability in FD SOI MOSFETs fall on the straight line. Their mechanisms are discussed based on three-dimensional (3D) device simulation considering random dopant fluctuation (RDF). It is found that the saturation of the COV and DIBL variability in smaller devices is caused by weaker averaging effect of channel potentials.

Gate Length and Gate Width Dependence of Drain Induced Barrier Lowering and Current-Onset Voltage Variability in Bulk and Fully Depleted Silicon-on-Insulator Metal Oxide Semiconductor Field Effect Transistors

This paper presents the statistical analysis of a newly found drain current variability component called “current-onset voltage” (COV) variability as well as drain induced barrier lowering (DIBL) variability in bulk and fully-depleted (FD) silicon-on-insulator (SOI) devices. Intensive variability measurement data show that gate length and gate width dependent COV variability and DIBL variability in bulk metal–oxide–semiconductor field effect transistors (MOSFETs) deviate from the straight line in the Pelgrom plot. On the other hand, COV variability and DIBL variability in FD SOI MOSFETs fall on the straight line. Their mechanisms are discussed based on three-dimensional (3D) device simulation considering random dopant fluctuation (RDF). It is found that the saturation of the COV and DIBL variability in smaller devices is caused by weaker averaging effect of channel potentials.

Additional-Body Effects in a Self-Aligned Deca-Nanometer Ultrathin-Body and Buried Oxide Silicon-on-Insulator Metal–Oxide–Semiconductor Field-Effect Transistor: A Three-Dimensional Simulation Study

In this paper, we numerically investigate the additional-body effects (ABEs) created by the isolation-last fabrication process of a self-aligned deca-nanometer ultrathin-body and buried oxide (UTBB) silicon-on-insulator (SOI) metal–oxide–semiconductor field-effect transistor (MOSFET). The reasons for the device's new electrical characteristics are also explained in detail. The additional silicon body volumes of the UTBB SOI MOSFET are found to improve the subthreshold swing and the on/off current ratio. The additional body has a negative effect, however, upon both the gate leakage current and the total gate capacitance, when compared with a standard UTBB SOI MOSFET.

Experimental Study on Electron Mobility in Accumulation-Mode Silicon-on-Insulator Metal–Oxide–Semiconductor Field-Effect Transistors

Junctionless, or accumulation-mode, metal–oxide–semiconductor field-effect transistors (MOSFETs), where the channel and source/drain doping types are the same, have attracted growing interests because of their simpler fabrication processes. However, carrier transport properties, in particular, mobility characteristics, in the junctionless silicon-on-insulator (SOI) MOSFETs have been less studied. Although higher mobility in accumulation-mode SOI MOSFETs has been reported, the physical mechanisms of the higher mobility have not yet been clarified. In this work, the physical mechanisms of higher mobility in accumulation-mode MOSFETs have been investigated. We fabricated junctionless SOI MOSFETs with a channel doping concentration of 1×1017 cm-3 and an SOI body thickness of 48 nm whose mobility is greater than the bulk universal mobility in spite of the high doping concentration in the channel. The drain current consists of two components: one in the accumulation layer and the other in the SOI body. The mobility of each component is evaluated separately. As a result, it is revealed that the total mobility is the weighted mean of the two mobility components, where carrier concentration is the weight.

Experimental Study on Electron Mobility in Accumulation-Mode Silicon-on-Insulator Metal–Oxide–Semiconductor Field-Effect Transistors

Junctionless, or accumulation-mode, metal–oxide–semiconductor field-effect transistors (MOSFETs), where the channel and source/drain doping types are the same, have attracted growing interests because of their simpler fabrication processes. However, carrier transport properties, in particular, mobility characteristics, in the junctionless silicon-on-insulator (SOI) MOSFETs have been less studied. Although higher mobility in accumulation-mode SOI MOSFETs has been reported, the physical mechanisms of the higher mobility have not yet been clarified. In this work, the physical mechanisms of higher mobility in accumulation-mode MOSFETs have been investigated. We fabricated junctionless SOI MOSFETs with a channel doping concentration of 1×1017 cm-3 and an SOI body thickness of 48 nm whose mobility is greater than the bulk universal mobility in spite of the high doping concentration in the channel. The drain current consists of two components: one in the accumulation layer and the other in the SOI body. The mobility of each component is evaluated separately. As a result, it is revealed that the total mobility is the weighted mean of the two mobility components, where carrier concentration is the weight.

High performance silicon-on-insulator based ion-sensitive field-effect transistor using high-k stacked oxide sensing membrane

High performance ion-sensitive field-effect transistors (ISFETs) were realized using silicon-on insulator substrate (SOI) and engineered sensing membrane. The engineered sensing membrane for the gate oxide was proposed to improve the chemical stability and obtain the enhanced output signal by stacking SiO2/HfO2/Al2O3 (OHA) layers. The SOI-metal–oxide–semiconductor field effect transistor (MOSFET) with the OHA gate oxide showed a high on/off current ratio of 1.8 × 1010 and a low subthreshold swing of 65 mV/dec. The SOI based ISFET with the OHA membrane exhibited a low drift rate of 0.23 mV/h, a low hysteresis width of 1.85 mV, and a high pH sensitivity level of 57.1 mV/pH.

Universal Relationship between Substrate Current and History Effect in Silicon-on-Insulator Metal–Oxide–Semiconductor Field-Effect Transistors

This paper presents an experimentally found device-size-independent universal relationship between the settling time of floating-body silicon-on-insulator (SOI) metal–oxide–semiconductor field-effect transistors (MOSFETs) and the substrate current in body-tied devices. Such a relationship could enable one to characterize dynamic properties of SOI MOSFETs through DC measurements and would be useful for physical compact modeling of history effects.

Ultra-low on-resistance high voltage (> 600 V) SOI MOSFET with a reduced cell pitch

A low specific on-resistance (RS,on) silicon-on-insulator (SOI) trench MOSFET (metal—oxide—semiconductor—field—effect—transistor) with a reduced cell pitch is proposed. The lateral MOSFET features multiple trenches: two oxide trenches in the drift region and a trench gate extended to the buried oxide (BOX) (SOI MT MOSFET). Firstly, the oxide trenches increase the average electric field strength along the x direction due to lower permittivity of oxide compared with that of Si; secondly, the oxide trenches cause multiple-directional depletion, which improves the electric field distribution and enhances the reduced surface field (RESURF) effect in the SOI layer. Both of them result in a high breakdown voltage (BV). Thirdly, the oxide trenches cause the drift region to be folded in the vertical direction, leading to a shortened cell pitch and a reduced RS,on. Fourthly, the trench gate extended to the BOX further reduces RS,on, owing to the electron accumulation layer. The BV of the MT MOSFET increases from 309 V for a conventional SOI lateral double diffused metal—oxide semiconductor (LDMOS) to 632 V at the same half cell pitch of 21.5 μm, and RS,on decreases from 419 mΩ·cm2 to 36.6 mΩ·cm2. The proposed structure can also help to dramatically reduce the cell pitch at the same breakdown voltage.

Threshold Voltage Dependence of Threshold Voltage Variability in Intrinsic Channel Silicon-on-Insulator Metal–Oxide–Semiconductor Field-Effect Transistors with Ultrathin Buried Oxide

Threshold voltage (Vth) variability due to random dopant fluctuations in intrinsic channel silicon-on-insulator (SOI) metal–oxide–semiconductor field-effect transistors (MOSFETs) with an ultrathin buried oxide is investigated by three-dimensional device simulation. It is found that, in contrast to bulk and doped channel SOI MOSFETs, Vth variations in intrinsic channel SOI MOSFETs decrease with increasing Vth. A device design guideline for intrinsic channel SOI MOSFETs is also discussed.

A noncharge-sheet channel potential and drain current model for dynamic-depletion silicon-on-insulator metal-oxide-semiconductor field-effect transistors

This paper presents a noncharge-sheet channel potential and drain current model for long-channel dynamic-depletion (DD) silicon-on-insulator (SOI) metal-oxide-semiconductor field-effect transistors (MOSFETs). Based on the Poisson–Boltzmann equation, an analytical solution of the channel potentials in the front, back silicon/oxide and substrate/oxide interfaces is developed. It is a universal solution which predicts the channel potential accurately in all cases from accumulation to strong inversion. A unified noncharge-sheet drain current expression is derived from the three-interface analysis based on the universal channel potential solution. The proposed model shows excellent agreements with two-dimensional numerical simulations with varying geometrical structures at different device operation regions. This model provides a useful tool to study the device physics and develop a complete compact model for DD SOI MOSFET.

Simulation of asymmetric doped high performance silicon on insulator metal oxide semiconductor field effect transistors for very large scale integrated complementary metal oxide semiconductor technologies

Asymmetric halo and extension implantations are examined by simulation for their usability in 45 and 32 nm technology high performance silicon on insulator metal oxide semiconductor field effect transistors (SOI-MOSFETs). Tilted halo and extension implantations from the source side show higher saturation currents and lower drain overlap and junction capacitances, which improve the intrinsic MOSFET power delay product. Furthermore the asymmetric doping profile leads to an inverter chain speed benefit. The stronger short channel effect, present in these devices, can be reduced by a low dose drain side halo implantation simultaneously maintaining a transistor performance improvement from asymmetric doping. This optimized transistor design is successfully transferred from the 45 into the 32 nm technology.

Equivalent Oxide Thickness of Trigate SOI MOSFETs With High-$\kappa$ Insulators

The evolution of traditional metal-oxide-semiconductor field-effect transistors (MOSFETs) from planar single-gate devices into 3-D ones with multiple gates and high-kappa insulators imposes the use of new electrical models that accurately reproduce their behavior. This paper demonstrates that the typical expression of equivalent oxide thickness (EOT) for planar devices with high- kappa gate insulators becomes useless for nonplanar ones such as triple-gate (trigate) silicon-on-insulator MOSFETs. An alternative expression of the EOT for these trigate devices has been developed through a semianalytical approach to the gate-insulator capacitance. The proposed model correctly reproduces the total electron density in a wide range of device dimensions and applied biases.

Two-Dimensional Analytical Modeling of Fully Depleted Short-Channel Dual-Gate Silicon-on-Insulator Metal Oxide Semiconductor Field Effect Transistor

In this paper, a two-dimensional (2D) analytical model of the surface potential variation along the channel in a fully depleted dual-gate (DG) silicon-on-insulator (SOI) metal oxide semiconductor field effect transistor (MOSFET) is proposed to investigate short-channel effects (SCEs). Our model includes the length of the two gates and the voltage difference between them. We demonstrate that the surface potential in the channel region exhibits a step function, which causes the screening of the drain potential. This results in suppressed SCEs such as the hot-carrier effect and drain-induced barrier lowering (DIBL). The obtained results of our model are compared with those of the single-gate (SG) SOI MOSFET, and the DG SOI MOSFET performance is found to be superior.

Physics of fluctuation processes in downscaled silicon MOSFETs

Physical mechanics of fluctuation processes in advanced submicron and decananometer MOSFETs (metal-oxide-semiconductor field-effect transistors) including the ultra-thin film SOI (siliconon-insulator) devices using strained silicon films are reviewed. The review is substantially based on the results obtained by the authors. It is shown that the following drastic changes occur in the nature and parameters of noise in such devices as a result of their downscaling when the gate oxide thickness and the channel length and width are decreased, the SOI substrates are used, the silicon film thickness is reduced, the film doping level is varied, the strained silicon films are employed, etc. Firstly, the Lorentzian components can appear in the current noise spectra. Those components are due to (i) electron tunneling from the valence band through the gate oxide in the SOI MOSFETs of a sufficiently thin gate oxide (LKE-Lorentzians); (ii) Nyquist fluctuations generated in the source and drain regions near the back Si/SiO2 interface in the SOI MOSFETs (BGI Lorentzians); (iii) electron exchange between the channel and some single trap in the gate oxide of the transistors with sufficiently small length and width of the channel (RTS Lorentzians). Secondly, the 1/f-noise level can increase due to (i) the appearance of recombination processes near the Si/SiO2 interface activated by the currents of electron tunneling from the valence band; (ii) an increase in the trap density in the gate oxide of the devices fabricated on the biaxially tensile-strained silicon films; (iii) the contribution of the 1/f fluctuations of the current flowing through the gate oxide as a result of electron tunneling from the conduction band. At the same time, the 1/f-noise level may decrease due to a decrease in the trap density in the gate oxide of the transistors fabricated on the uniaxially tensile-strained silicon films. Moreover, a 1/f 1.7 component may appear in the noise spectra for the transistors of a sufficiently thin gate oxide, whose component is due to charge fluctuations on the defects located near the interface between the gate polysilicon and the gate oxide. Thus, the main physical mechanics of fluctuation processes in advanced submicron and decananometer MOSFETs are considered and it is shown by what physical reasons and how the downscaling of MOSFETs affects their fluctuation characteristics.

Electrical Characteristics and Crystal Quality Analysis of Thin-Body Channel Silicon-on-Insulator Metal–Oxide–Semiconductor Field-Effect Transistors Using Two-Step Elevated Silicon Epitaxial Process

A two-step source/drain elevated epitaxial process for ultra thin fully depleted (FD) silicon-on-insulator (SOI) metal–oxide–semiconductor field-effect transistors (MOSFETs) is proposed. The relation between the crystal quality of the source/drain extension regions and channel orientation with the silicon epitaxial process is analyzed by transmission electron microscopy (TEM). No defect is observed in the source/drain extension regions on the <100> channel, whereas crystal defects are observed on the <110> channel. Crystal defect generation in the source/drain extension regions is closely related to channel orientation. Moreover, a low parasitic resistance of thin-body SOI MOSFETs is realized in <100> channel SOI-MOSFET, and high Ion(Ids)–Ioff characteristics and the suppression of the roll-off characteristics of thin-body SOI MOSFETs with the <100> channel orientation are shown. It is confirmed that thin-body SOI MOSFETs with a two-step source/drain elevated epitaxial process have a high potential for the application in the 22 nm generation.