Abstract
In this paper, a two-dimensional (2D) analytical model of the surface potential variation along the channel in a fully depleted dual-gate (DG) silicon-on-insulator (SOI) metal oxide semiconductor field effect transistor (MOSFET) is proposed to investigate short-channel effects (SCEs). Our model includes the length of the two gates and the voltage difference between them. We demonstrate that the surface potential in the channel region exhibits a step function, which causes the screening of the drain potential. This results in suppressed SCEs such as the hot-carrier effect and drain-induced barrier lowering (DIBL). The obtained results of our model are compared with those of the single-gate (SG) SOI MOSFET, and the DG SOI MOSFET performance is found to be superior.
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