Silicon-on-insulator Lateral Insulated Gate Bipolar Transistor Research Articles

Improvement in U-Shaped Channel SOI Lateral IGBT for Wider Reverse Bias Safe Operating Area

In this article, the inductive turn-off failure mechanism of U-shaped channel silicon-on-insulator lateral insulated-gate bipolar transistor (SOI-LIGBT) under high-voltage and high-current is investigated by experiments and numerical simulations. First, the measured turn-off waveforms before and after failure are compared to infer the cause of the failure. Then, the failure is reproduced by calibrated three-dimensional simulations using Sentaurus TCAD. According to the simulation and measured results, the turn-off failure is resulted from the high impact ionization in the bird’s beak region. To reveal the failure mechanism, the turn-off failure process is divided into two phases. In phase I, the electrons generated by drastic impact ionization in the bird’s beak region act as the base current to keep the operation of parasitic PNP transistor after channel pinching off. In phase II, the parasitic NPN transistor is activated due to the hole current amplified by PNP, and thus, turn-off failure occurs. Based on the revealed turn-off failure mechanism, an improved U-shaped channel SOI-LIGBT with a P-top is proposed. The P-top is arranged in the bird’s beak region to reduce the impact ionization rate. The measured results demonstrate that no failure occurs when the improved device turns off under high-voltage and high-current conditions. Compared with the conventional U-shaped channel SOI-LIGBT, the improved device obtains 275% and 23% improvements in turn-off current at a bus voltage of 450 V and reverse bias safe operation area, respectively.

Fast-switching SOI-LIGBT with compound dielectric buried layer and assistant-depletion trench

A lateral insulated gate bipolar transistor (LIGBT) based on silicon-on-insulator (SOI) structure is proposed and investigated. This device features a compound dielectric buried layer (CDBL) and an assistant-depletion trench (ADT). The CDBL is employed to introduce two high electric field peaks that optimize the electric field distributions and that, under the same breakdown voltage (BV) condition, allow the CDBL to acquire a drift region of shorter length and a smaller number of stored carriers. Reducing their numbers helps in fast-switching. Furthermore, the ADT contributes to the rapid extraction of the stored carriers from the drift region as well as the formation of an additional heat-flow channel. The simulation results show that the BV of the proposed LIGBT is increased by 113% compared with the conventional SOI LIGBT of the same length L D. Contrastingly, the length of the drift region of the proposed device (11.2 μm) is about one third that of a traditional device (33 μm) with the same BV of 141 V. Therefore, the turn-off loss (E OFF) of the CDBL SOI LIGBT is decreased by 88.7% compared with a conventional SOI LIGBT when the forward voltage drop (V F) is 1.64 V. Moreover, the short-circuit failure time of the proposed device is 45% longer than that of the conventional SOI LIGBT. Therefor, the proposed CDBL SOI LIGBT exhibits a better V F–E OFF tradeoff and an improved short-circuit robustness.

Simulation Study of Novel Trench Gate U-Shaped Channel SOI Lateral IGBTs With Suppressed Gate Voltage Overshoot and Reduced di/dt

The gate voltage overshoot during the turn-on transient in the trench gate U-shaped (TGU) channel silicon-on-insulator lateral insulated gate bipolar transistor (SOI-LIGBT) is investigated and novel structures are proposed for the first time with numerical simulation in this article. The TGU SOI-LIGBT features two U-shaped trench gates, G <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</sub> and G <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> , connected together. The U-shaped trench for G <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> serves as a hole barrier trench. A large number of holes accumulate in the U-shaped region during the turn-on transient because of the U-shaped architecture and the hole-blocking effect of G <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> . The displacement current induced by the nonuniform distributed holes overcharges the gate and leads to high di/dt. In this article, the novel structures (Novel-1 and Novel-2) with G <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> partially filled by the polysilicon are proposed for the improvement in gate voltage overshoot while keeping superior turn-on loss ( E <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> ON</sub> ). The novel structures (Novel-1 and Novel-2) can suppress the hole accumulation and slow down the rising of the electric potential in the silicon region near the G <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> . The di/dt can be lowered and the displacement current that overcharges G <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> can be effectively shielded. Compared with the conventional TGU structure, the di/dt of the Novel-2 are improved by 56.3% at the same E <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> ON</sub> of 2.4 mJ/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

Experimental investigation on total-ionizing-dose radiation effects on the electrical properties of SOI-LIGBT

In this paper, the experimental investigation on the electrical properties of silicon-on-insulator lateral insulated-gate bipolar transistor (SOI-LIGBT) after total-ionizing-dose (TID) irradiation is presented. We find that the TID irradiation reduces the threshold voltage (Vth), and increases the collector current (ICE) at the same gate voltage (Vg). The raising ICE is mainly attributed to the negative shift of the Vth. However, at the same overdrive voltage (Vov = Vg − Vth), the ICE at small VCE increases and the ICE at high VCE decreases after irradiation. The distinctive response of the out-put characteristics after irradiation is ascribed to the positive trapped charges in the field oxide (FOX) layer and the buried oxide (BOX) layer. The inimitable out-put behavior occurs at whatever the sign of the gate bias voltage during irradiation. The degradation mechanisms of the TID effects on the SOI-LIGBT are further analyzed and confirmed by simulation.

A Novel No Miller Plateau SOI-LIGBT With Low Saturation Current and Improved Switching Performance

This article proposes a new idea to improve the $\text{d}{I}/\text{d}{t}$ and $\text{d}{V}/\text{d}{t}$ controllability of the lateral insulated gate bipolar transistor (LIGBT). By employing an inversion layer thyristor T to enhance the conductivity modulation and applying the startup nMOS M4 with small Miller capacitance, the proposed LIGBT not only realizes low saturation current, but also eliminates the Miller plateau. The simulation results demonstrate that the saturation current with a value of 682 A/cm2 is reduced by 55.5%, and the short-circuit time is improved by 375% in comparison with that of the self-adjust conductivity modulation LIGBT (SCM-LIGBT) silicon-on-insulator LIGBT (SOI-LIGBT). Especially, the $\text{d}{V}/\text{d}{t}$ and $\text{d}{I}/\text{d}{t}$ controllability are improved by 21% and 49%, respectively, since the Miller plateau is basically eliminated.

A Novel Low on-State Voltage SOI LIGBT With Enhanced Conductivity Modulation

A novel composite device structure with enhanced conductivity modulation silicon on insulator (SOI) lateral insulated gate bipolar transistor (LIGBT) which consists of a normal LIGBT (NLT) region, an nMOS region (NM) and a pMOS region (PM) is proposed in this article. By employing a parasitic n-p-n bipolar transistor, the thyristor in the NLT performs a high electron current in ON-state. As a result, the conductivity modulation in the NLT region is dramatically enhanced, which leads to the improvement of the current capability and the forward ON-state voltage drop. In addition, due to the parasitic diode in the substrate of NM, the potential of p-base of the NLT can be clamped at the ON-state voltage drop of the diode, which guarantees the current saturated capability of the LIGBT.

Turn-Off Transient of Superjunction SOI Lateral IGBTs: Mechanism and Optimization Strategy

In this paper, five types of superjunction (SJ) configurations are investigated in the silicon-on-insulator lateral insulated-gate bipolar transistor (SOI-LIGBT). technology computer aided design simulations are carried out to give insight into the mechanism for improving turn-off loss ( ${E} _{ \mathrm{\scriptscriptstyle OFF}}$ ) by adopting SJ in the drift region of SOI-LIGBT. In mechanism revealing, collector–emitter voltage rising during the inductive load turn-off is divided into two phases: slow rising phase (SRP) and rapid rising phase (RRP). It is found that the depletion accompanying with carrier extraction in the drift region and at the collector is responsible for the SRP and RRP, respectively, and accordingly, the difference of turn-off transient among the five types of SJ configurations is clarified. Moreover, reduced ${E} _{ \mathrm{\scriptscriptstyle OFF}}$ can be realized by lowering the transition voltage from SRP to RRP ( ${V} _{\text {A}}$ ). Low electric potential from the emitter side can be delivered to the collector side through the undepleted regions in P-pillar, which largely determine ${V} _{\text {A}}$ . According to the above-mentioned mechanism, an optimization strategy and a novel SJ SOI-LIGBT with composite P-pillar are proposed for the first time. The proposed SJ SOI-LIGBT achieves an ${E} _{ \mathrm{\scriptscriptstyle OFF}}~76.3$ % lower than the conventional SOI-LIGBT at ON-state voltage drop of ~1.41 V.

500-V Silicon-On-Insulator Lateral IGBT With W-Shaped n-Typed Buffer and Composite p-Typed Collectors

A novel 500-V rated silicon-on-insulator lateral insulated-gate bipolar transistor (SOI-LIGBT), featuring a W-shaped n-typed buffer and p-typed composite collectors, is proposed for the first time in this paper. The composite collectors which consist of a high-doped p+ layer and a low-doped p− layer can maintain a high level of collector-side hole injection in ON-state; the low-doped p− layer combining with the W-shaped buffer provides a low barrier path for electron extraction during turn-off; thus, high current capability and high turn-off speed can be realized at the same time. The measurement results show that 67.3% decrease in turn-off time can be obtained at the expense of only 6.3% of current capability. Compared with the standard SOI-LIGBT, no additional processing steps or process modifications are required for the proposed SOI-LIGBT. The low-doped p− collector is formed simultaneously with the emitter-side p-well while the W-shaped buffer is formed by diffusion overlapping of two neighboring windows. At 125 °C, the proposed SOI-LIGBT exhibits an ON-state voltage drop of 2.48 V, a saturated current density of 420 A/cm2, a turn-off time of $>4~\mu \text{s}$ , allowing significant improvements in power loss, operating frequency, and ruggedness for single-chip intelligent power ICs.

A New Low Turn-Off Loss SOI Lateral Insulated Gate Bipolar Transistor With Buried Variation of Lateral Doping Layer

In this paper, we propose a new low turn-off loss silicon-on-insulator (SOI) lateral insulated gate bipolar transistor (LIGBT) with buried variation of lateral doping (VLD) layer. The proposed device features a VLD layer inserted in the drift region, which increases the doping dose ( Q ) and gradient ( G ) compared with Uniform P-buried (UPB) SOI LIGBT. The larger capacitance effect induced by lager Q and faster depletion leads to the lower rising anode voltage and reduced storage charge in the drift region. Therefore, a considerable low turn-off loss ( E off) can be obtained. It is worth to note that owing to reshaped electric field in the new structure, the excess carriers of the drift region could be removed more quickly. Furthermore, larger G of the VLD layer improves the tradeoff between breakdown voltage and turn-off loss. The results of 2-D simulation indicate that the E off of the proposed device can reduce by 29.4% and 69.7% at 100 A $\cdot$ cm−2 and 200 A $\cdot$ cm−2, respectively, when compared with UPB SOI LIGBT

Optimization of &lt;inline-formula&gt; &lt;tex-math notation="LaTeX"&gt;${V}_{\text{CE}}$ &lt;/tex-math&gt; &lt;/inline-formula&gt; Plateau for Deep-Oxide Trench SOI Lateral IGBT During Inductive Load Turn-OFF

Collector–emitter voltage ( ${V}_{\textsf {CE}}$ ) plateau of the 500-V deep-oxide trench (DOT) silicon-on-insulator lateral insulated gate bipolar transistor (SOI-LIGBT) during inductive load turn-off is investigated and optimized for the first time in this paper, aiming to reduce the turn-off loss ( ${E}_{ \mathrm{\scriptscriptstyle OFF}}$ ). The mechanism of ${V}_{\textsf {CE}}$ plateau is revealed by TCAD simulation. In conventional DOT SOI-LIGBT, the large number of stored carries in the silicon region beneath the DOT (Region I) hinders the extension of depletion layer and slows down ${V}_{\textsf {CE}}$ rising during turn-off, leading to a plateau phase. A novel DOT SOI-LIGBT with dual-controllable vertical field plates (CPFs) is proposed to shorten the ${V}_{\textsf {CE}}$ plateau. The dual CPFs are arranged in the DOT and their electric potentials ( ${V}_{\textsf {F} 1}$ and ${V}_{\textsf {F} 2}$ ) are controlled through the connection with scrolled resistive polysilicon filed plate. By adjusting ${V}_{\textsf {F} 1}$ and ${V}_{\textsf {F} 2}$ , the accelerated depletion and extraction of stored carriers in Region I can be realized, resulting in a short ${V}_{\mathbf {CE}}$ plateau duration. The ${V}_{\mathbf {CE}}$ plateau duration can be decreased from 156 ns for the conventional SOI-LIGBT to 60 ns for the proposed SOI-LIGBT with ${V}_{F1} = 0$ V and ${V}_{\textsf {F}2} = {0.5}\,\,{V}_{\textsf {CE}}$ . The proposed DOT SOI-LIGBT achieves an ${E}_{ \mathrm{\scriptscriptstyle OFF}} $ 59.2% lower than the conventional DOT SOI-LIGBT at the same ${V}_{ \mathrm{\scriptscriptstyle ON}}$ of 2.96 V.

Influence of Latch-Up Immunity Structure on ESD Robustness of SOI-LIGBT Used As Output Device

The influences of three typical latch-up immunity structures, including high concentrated P++ doping layer, N+/P+ segmented emitter and P-sink well, upon electro-static discharge (ESD) robustness of the silicon-on-insulator lateral insulated gate bipolar transistor (SOI-LIGBT) devices are compared. The high concentrated P++ doping layer makes the SOI-LIGBT have the weakest ESD robustness, because the slow turn-on speed of parasitic n-p-n transistor brings long-time high power state and heat accumulation. The N+/P+ segmented emitter causes the SOI-LIGBT to own the medium ESD robustness and the SOI-LIGBT fails at the emitter side due to the crowded current made by the small N+ emitter region. For the P-sink well, it makes SOI-LIGBT exhibit the strongest ESD robustness, because the current can flow along the P-sink into the emitter vertically, which is helpful for reducing surface current density. Considering the comprehensive performances, the P-sink well is suggested as the latch-up immunity structure, which guarantees high latch-up immunity ability and strong ESD robustness simultaneously.

Low-Loss SOI-LIGBT With Triple Deep-Oxide Trenches

A novel 500-V silicon-on-insulator lateral insulated gate bipolar transistor (SOI-LIGBT) is proposed for the first time in this paper. The device features triple deep oxide trenches (TDOT) arranged in the drift region. The depths of the trenches near the emitter side (T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">E</sub> ) and near the collector side (T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">C</sub> ) are shallower than that of the trench (T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">M</sub> ) located in the silicon region between T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">E</sub> and T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">C</sub> . Compared with a reported SOI-LIGBT with dual deep-oxide trenches (DDOT), the shallow trench near the emitter side (T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">E</sub> ) in the proposed TDOT SOI-LIGBT alleviates the JFET effect between the P-body region and T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">E</sub> , resulting in a lower on-state voltage drop (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> ). In the off-state, the electric potential sustained by the TDOT is higher than that of the DDOT. At the same breakdown voltage of 560 V, the length of silicon region between T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">C</sub> and N-buffer region (L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> ) is reduced from 9 μm for the DDOT SOI-LIGBT to 5 μm for the proposed TDOT SOI-LIGBT, indicating a smaller number of stored carries at the collector side and thereby a faster turn-off in the proposed TDOT SOI-LIGBT. The experiments demonstrate that the proposed TDOT SOI-LIGBT achieves turn-off loss (E <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</sub> ) 36.1% lower than the DDOT SOI-LIGBT at the same V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> of 1.53 V.

Low-Loss SOI-LIGBT With Dual Deep-Oxide Trenches

A novel 500-V silicon-on-insulator lateral insulated gate bipolar transistor (SOI-LIGBT) is proposed for the first time in this paper. The device features triple deep-oxide trenches (TDOT) arranged in the drift region. The depths of the trenches near the emitter side ( ${T}_{\textit {E}})$ and near the collector side ( ${T}_{\textit {C}})$ are shallower than that of the trench ( ${T}_{\textit {M}})$ located in the silicon region between ${T}_{\textit {E}}$ and $T_{\textit {C}}$ . Compared with a reported SOI-LIGBT with dual deep-oxide trenches (DDOT), the shallow trench near the emitter side ( ${T}_{\textit {E}})$ in the proposed TDOT SOI-LIGBT alleviates the JFET effect between the P-body region and ${T}_{\textit {E}}$ , resulting in a lower on-state voltage drop ( ${V} _\mathrm{on})$ . In the off-state, the electric potential sustained by the TDOT is higher than that of the DDOT. At the same breakdown voltage of 560 V, the length of silicon region between $T_{C}$ and N-buffer region ( ${L} _{2})$ is reduced from $9~\mu \text{m}$ for the DDOT SOI-LIGBT to $5~\mu \text{m}$ for the proposed TDOT SOI-LIGBT, indicating a smaller number of stored carries at the collector side and thereby a faster turn-off in the proposed TDOT SOI-LIGBT. The experiments demonstrate that the proposed TDOT SOI-LIGBT achieves turn-off loss ( $\text{E}_{\text {OFF}})~36.1$ % lower than the DDOT SOI-LIGBT at the same ${V}_{\mathrm{on}}$ of 1.53 V.

Turn-off failure in multi-finger SOI-LIGBT used for single chip inverter ICs

In this paper, the clamped inductive turn-off failure of the Silicon-on-Insulator Lateral Insulated Gate Bipolar Transistor (SOI-LIGBT) with multiple fingers under high-voltage and high-current conditions is investigated. First, the measured turn-off waveforms combining with the on-state I-V characteristics of the failed device are discussed to distinguish the probable cause of the failure. Then, two-dimensional (2-D) electrothermal simulations are performed to reproduce the failure by using Sentaurus TCAD. The failure is originated from an inhomogeneous depletion behavior among the paralleled fingers during the turn-off, which gives rise to the non-uniform current-sharing and the subsequent current crowding in single finger. As a result, the latch-up of the device takes place. The simulation indicates that the current crowding is formed mainly through an internal path in the silicon. In order to verify the failure mechanism, an improved device with deep-oxide trenches arranged between the adjacent fingers is fabricated. The measured results demonstrate that no failure occurs when the improved device turns off under high-voltage and high-current conditions.

A U-Shaped Channel SOI-LIGBT With Dual Trenches

This paper proposes a U-shaped channel silicon-on-insulator lateral insulated gate bipolar transistor (SOI-LIGBT) with dual trenches to reduce the turn-off loss while keep the low ON-state voltage drop. The device features a U-shaped gate trench (G1) and a U-shaped hole-barrier trench (G2). By introducing the dual trenches, enhanced carrier stored effect at the emitter side, more uniform carrier distribution in the drift region, and low carrier density at the collector are realized, resulting in decreases of ON-state voltage drop ( ${V}_{\mathrm{\scriptscriptstyle ON}}$ ) and turn-OFF loss ( ${E}_{\mathrm{\scriptscriptstyle OFF}})$ . The proposed SOI-LIGBT offers an ${E}_{\mathrm{\scriptscriptstyle OFF}}~52.3$ % lower than the conventional planar-gate U-shaped channel SOI-LIGBT at the same ${V}_{\mathrm{\scriptscriptstyle ON}}$ of 1.22 V. Moreover, the proposed SOI-LIGBT exhibits a latch-up free characteristic at the current density larger than 1200 A/cm2.

A new high-voltage interconnection shielding method for SOI monolithic ICs

The high-voltage interconnection (HVI) issue becomes severe in the high-voltage monolithic ICs when single-layer metal is used for lowering the cost. This paper proposes a dual deep-oxide trenches (DDOT) structure for 500V Silicon-on-Insulator Lateral Insulated Gate Bipolar Transistor (SOI-LIGBT) to shield the influence of HVI on the breakdown voltage. Compared with the conventional DDOT structure, HVI region of the proposed DDOT structure is shrunk by employing a shallow trench (T1) and a deep trench (T2). Besides the breakdown mechanism in the off-state, the current density and impact ionization rate distributions in the on-state of the proposed structure are also investigated. The experiments demonstrate that the proposed DDOT structure can fully shield the influence of HVI with significant reduction in the area of silicon region beneath the HVI. With almost the same off-state breakdown voltage (BVoff) of 550V as the conventional DDOT structure, the length of the silicon region under the HVI in the proposed structure is shortened from 45μm to 15μm. Meanwhile, no on-state breakdown voltage (BVon) degradation is observed according to the measured results. The new method proposed in this work can also be used for other types of high-voltage devices such as LDMOS and free-wheeling diode in SOI Monolithic ICs.

Novel Snapback-Free Reverse-Conducting SOI-LIGBT With Dual Embedded Diodes

A novel 500 V reverse-conducting (RC) silicon-on-insulator lateral insulated gate bipolar transistor (SOI-LIGBT) with dual embedded diodes (DEDs) is proposed to eliminate the snapback, and its mechanism is investigated by simulation. The RC is realized by the internal diode, which consists of two p-i-n diodes (D1 and D2). The two diodes are connected in series. In the RC-state, the current flows through D1 first and then through D2. D2 is embedded in the anode region of the proposed DED-LIGBT and is fully isolated by the deep-oxide trench. In the forward conducting state, D2 is reverse biased and the electrons from the N+ cathode can only flow into the P+ anode. The DEDs reroute the electron current path, and thus, the snapback is avoided. Moreover, by adjusting the width of D2 ( ${W}_{b})$ , the internal diode of the DED structure achieves superior reverse recovery time ( ${t}_{\text {rr}})$ and reverse recovery peak current ( ${I}_{\text {rrm}})$ to the conventional SOI p-i-n diode.

Ultralow turnoff loss dual-gate SOI LIGBT with trench gate barrier and carrier stored layer**Project supported by the National Natural Science Foundation of China (Grant Nos. 61376080 and 61674027) and the Natural Science Foundation of Guangdong Province, China (Grant Nos. 2014A030313736 and 2016A030311022).

A novel ultralow turnoff loss dual-gate silicon-on-insulator (SOI) lateral insulated gate bipolar transistor (LIGBT) is proposed. The proposed SOI LIGBT features an extra trench gate inserted between the p-well and n-drift, and an n-type carrier stored (CS) layer beneath the p-well. In the on-state, the extra trench gate acts as a barrier, which increases the carrier density at the cathode side of n-drift region, resulting in a decrease of the on-state voltage drop (Von). In the off-state, due to the uniform carrier distribution and the assisted depletion effect induced by the extra trench gate, large number of carriers can be removed at the initial turnoff process, contributing to a low turnoff loss (Eoff). Moreover, owing to the dual-gate field plates and CS layer, the carrier density beneath the p-well can greatly increase, which further improves the tradeoff between Eoff and Von. Simulation results show that Eoff of the proposed SOI LIGBT can decrease by 77% compared with the conventional trench gate SOI LIGBT at the same Von of 1.1 V.

Further Study of the U-Shaped Channel SOI-LIGBT With Enhanced Current Density for High-Voltage Monolithic ICs

A high-voltage silicon-on-insulator lateral insulated-gate bipolar transistor (SOI-LIGBT) with U-shaped channels, which are composed of parallel channels and orthogonal channels for improving the current density ( $J_{C}$ ) and latch-up immunity, is proposed and studied intensively in this paper. By using the U-shaped channels, the electron injection from the emitter into the $n$ -drift region is significantly enhanced, and the current density is improved. In addition, an analytical model is proposed, and it is indicated that $J_{C}$ can be improved as $\alpha $ (the angle between the parallel channel and the orthogonal channel) increases in a certain range. The hole current density distribution in the ON-state and the lattice temperature distribution in the short-circuit state of the proposed structure are also investigated. Increasing $\alpha $ is beneficial to alleviate the holes crowding beneath the n+ emitter and suppress the temperature rise in the JFET region, which is favorable for increasing the latch-up voltage ( $V_{\textrm {LP}}$ ) and short-circuit withstand time ( $t_{\textrm {SC}}$ ). The experiments demonstrate that the U-shaped channel SOI-LIGBT fabricated with 0.5- $\mu \text{m}$ SOI technology exhibits a high current density ( $J_{C}$ ) of 305 A/cm2 at $V_{\textrm {CE}}=3$ V and $V_{\textrm {GE}}=5$ V, and a low specific ON-resistance ( $R_{{\mathrm{\scriptscriptstyle ON}}\,\cdot \,\textrm {sp}}$ ) of 0.984 $\Omega \cdot \textrm {mm}^{2}$ with breakdown voltage of 590 V. The improved latch-up voltage ( $V_{\textrm {LP}}$ ) of 560 V and the short-circuit withstand time ( $t_{\textrm {SC}}$ ) of 5.1 $\mu \text{s}$ are obtained.

Cost-effective mask-sharing technology for SOI LIGBT and PLDMOS

Cost-effective mask-sharing technology for the 200 V silicon-on-insulator (SOI) lateral insulated gate bipolar transistor (LIGBT) and p-channel lateral double-diffused MOS (PLDMOS) are proposed in this paper. N-well and P-body implantations are shared as an N-buffer implantation of the LIGBT and P-buffer implantation of the PLDMOS, respectively, which reduces two masks compared with the conventional process. The structure and process parameters for LIGBT and PLDMOS with the new process are optimized by simulation to achieve good performance. The experimental results indicate that the LIGBT and PLDMOS using the new process maintain the same performance compared to the conventional devices.